1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Definition of BaseCache functions.
46 */
47
48#include "mem/cache/base.hh"
49
50#include "debug/Cache.hh"
51#include "debug/Drain.hh"
52#include "mem/cache/cache.hh"
53#include "mem/cache/mshr.hh"
54#include "mem/cache/tags/fa_lru.hh"
55#include "sim/full_system.hh"
56
57using namespace std;
58
59BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
60 BaseCache *_cache,
61 const std::string &_label)
62 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
63 blocked(false), mustSendRetry(false),
64 sendRetryEvent([this]{ processSendRetry(); }, _name)
65{
66}
67
68BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
69 : MemObject(p),
70 cpuSidePort(nullptr), memSidePort(nullptr),
71 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
72 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
73 blkSize(blk_size),
74 lookupLatency(p->tag_latency),
75 dataLatency(p->data_latency),
76 forwardLatency(p->tag_latency),
77 fillLatency(p->data_latency),
78 responseLatency(p->response_latency),
79 numTarget(p->tgts_per_mshr),
80 forwardSnoops(true),
81 isReadOnly(p->is_read_only),
82 blocked(0),
83 order(0),
84 noTargetMSHR(nullptr),
85 missCount(p->max_miss_count),
86 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
87 system(p->system)
88{
89 // the MSHR queue has no reserve entries as we check the MSHR
90 // queue on every single allocation, whereas the write queue has
91 // as many reserve entries as we have MSHRs, since every MSHR may
92 // eventually require a writeback, and we do not check the write
93 // buffer before committing to an MSHR
94
95 // forward snoops is overridden in init() once we can query
96 // whether the connected master is actually snooping or not
97}
98
99void
100BaseCache::CacheSlavePort::setBlocked()
101{
102 assert(!blocked);
103 DPRINTF(CachePort, "Port is blocking new requests\n");
104 blocked = true;
105 // if we already scheduled a retry in this cycle, but it has not yet
106 // happened, cancel it

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131 // reset the flag and call retry
132 mustSendRetry = false;
133 sendRetryReq();
134}
135
136void
137BaseCache::init()
138{
139 if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
140 fatal("Cache ports on %s are not connected\n", name());
141 cpuSidePort->sendRangeChange();
142 forwardSnoops = cpuSidePort->isSnooping();
143}
144
145BaseMasterPort &
146BaseCache::getMasterPort(const std::string &if_name, PortID idx)
147{
148 if (if_name == "mem_side") {
149 return *memSidePort;
150 } else {
151 return MemObject::getMasterPort(if_name, idx);
152 }
153}
154
155BaseSlavePort &
156BaseCache::getSlavePort(const std::string &if_name, PortID idx)
157{
158 if (if_name == "cpu_side") {
159 return *cpuSidePort;
160 } else {
161 return MemObject::getSlavePort(if_name, idx);
162 }
163}
164
165bool
166BaseCache::inRange(Addr addr) const
167{
168 for (const auto& r : addrRanges) {
169 if (r.contains(addr)) {
170 return true;
171 }
172 }
173 return false;
174}
175
176void
177BaseCache::regStats()
178{
179 MemObject::regStats();
180
181 using namespace Stats;
182
183 // Hit statistics
184 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {

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758 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
759 }
760
761 replacements
762 .name(name() + ".replacements")
763 .desc("number of replacements")
764 ;
765}