1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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87 system(p->system)
88{
89}
90
91void
92BaseCache::CacheSlavePort::setBlocked()
93{
94 assert(!blocked);
95 DPRINTF(CachePort, "Cache port %s blocking new requests\n", name());
96 blocked = true;
97 // if we already scheduled a retry in this cycle, but it has not yet
98 // happened, cancel it
99 if (sendRetryEvent.scheduled()) {
100 owner.deschedule(sendRetryEvent);
101 DPRINTF(CachePort, "Cache port %s deschedule retry\n", name());
102 mustSendRetry = true;
103 }
104}
105
106void
107BaseCache::CacheSlavePort::clearBlocked()
108{
109 assert(blocked);
110 DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
111 blocked = false;
112 if (mustSendRetry) {
113 // @TODO: need to find a better time (next bus cycle?)
114 owner.schedule(sendRetryEvent, curTick() + 1);
115 }
116}
117
118void
119BaseCache::CacheSlavePort::processSendRetry()
120{
121 DPRINTF(CachePort, "Cache port %s sending retry\n", name());
122
123 // reset the flag and call retry
124 mustSendRetry = false;
125 sendRetryReq();
126}
127
128void
129BaseCache::init()

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