1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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101
102void
103BaseCache::CacheSlavePort::clearBlocked()
104{
105 assert(blocked);
106 DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
107 blocked = false;
108 if (mustSendRetry) {
109 DPRINTF(CachePort, "Cache port %s sending retry\n", name());
110 mustSendRetry = false;
111 // @TODO: need to find a better time (next bus cycle?)
112 owner.schedule(sendRetryEvent, curTick() + 1);
113 }
114}
115
116
117void
118BaseCache::init()
119{
120 if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
121 fatal("Cache ports on %s are not connected\n", name());
122 cpuSidePort->sendRangeChange();
123}
124

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