1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('Cache.py')
34
35Source('base.cc')
36Source('blk.cc')
37Source('cache.cc')
38Source('mshr.cc')
39Source('mshr_queue.cc')
40Source('noncoherent_cache.cc')
41Source('write_queue.cc')
42Source('write_queue_entry.cc')
43
44DebugFlag('Cache')
45DebugFlag('CachePort')
46DebugFlag('CacheRepl')
47DebugFlag('CacheTags')
48DebugFlag('CacheVerbose')
49DebugFlag('HWPrefetch')
50
51# CacheTags is so outrageously verbose, printing the cache's entire tag
52# array on each timing access, that you should probably have to ask for
53# it explicitly even above and beyond CacheAll.
54CompoundFlag('CacheAll', ['Cache', 'CachePort', 'CacheRepl', 'CacheVerbose',
55 'HWPrefetch'])
56