Cache.py (13892:0182a0601f66) Cache.py (13945:a573bed35a8b)
1# Copyright (c) 2012-2013, 2015, 2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 30 unchanged lines hidden (view full) ---

39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.params import *
43from m5.proxy import *
44from m5.SimObject import SimObject
45
46from m5.objects.ClockedObject import ClockedObject
1# Copyright (c) 2012-2013, 2015, 2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 30 unchanged lines hidden (view full) ---

39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.params import *
43from m5.proxy import *
44from m5.SimObject import SimObject
45
46from m5.objects.ClockedObject import ClockedObject
47from m5.objects.Compressors import BaseCacheCompressor
47from m5.objects.Prefetcher import BasePrefetcher
48from m5.objects.ReplacementPolicies import *
49from m5.objects.Tags import *
50
48from m5.objects.Prefetcher import BasePrefetcher
49from m5.objects.ReplacementPolicies import *
50from m5.objects.Tags import *
51
51
52# Enum for cache clusivity, currently mostly inclusive or mostly
53# exclusive.
54class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
55
56class WriteAllocator(SimObject):
57 type = 'WriteAllocator'
58 cxx_header = "mem/cache/cache.hh"
59

--- 40 unchanged lines hidden (view full) ---

100 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
101 prefetch_on_access = Param.Bool(False,
102 "Notify the hardware prefetcher on every access (not just misses)")
103
104 tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
105 replacement_policy = Param.BaseReplacementPolicy(LRURP(),
106 "Replacement policy")
107
52# Enum for cache clusivity, currently mostly inclusive or mostly
53# exclusive.
54class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
55
56class WriteAllocator(SimObject):
57 type = 'WriteAllocator'
58 cxx_header = "mem/cache/cache.hh"
59

--- 40 unchanged lines hidden (view full) ---

100 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
101 prefetch_on_access = Param.Bool(False,
102 "Notify the hardware prefetcher on every access (not just misses)")
103
104 tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
105 replacement_policy = Param.BaseReplacementPolicy(LRURP(),
106 "Replacement policy")
107
108 compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
109
108 sequential_access = Param.Bool(False,
109 "Whether to access tags and data sequentially")
110
111 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
112 mem_side = MasterPort("Downstream port closer to memory")
113
114 addr_ranges = VectorParam.AddrRange([AllMemory],
115 "Address range for the CPU-side port (to allow striping)")

--- 42 unchanged lines hidden --- 		110 sequential_access = Param.Bool(False,
111 "Whether to access tags and data sequentially")
112
113 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
114 mem_side = MasterPort("Downstream port closer to memory")
115
116 addr_ranges = VectorParam.AddrRange([AllMemory],
117 "Address range for the CPU-side port (to allow striping)")

--- 42 unchanged lines hidden ---