| Cache.py (13665:9c7fe3811b88) | Cache.py (13892:0182a0601f66) |
|---|---|
| 1# Copyright (c) 2012-2013, 2015, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 29 unchanged lines hidden (view full) --- 38# 39# Authors: Nathan Binkert 40# Andreas Hansson 41 42from m5.params import * 43from m5.proxy import * 44from m5.SimObject import SimObject 45 | 1# Copyright (c) 2012-2013, 2015, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 29 unchanged lines hidden (view full) --- 38# 39# Authors: Nathan Binkert 40# Andreas Hansson 41 42from m5.params import * 43from m5.proxy import * 44from m5.SimObject import SimObject 45 |
| 46from m5.objects.MemObject import MemObject | 46from m5.objects.ClockedObject import ClockedObject |
| 47from m5.objects.Prefetcher import BasePrefetcher 48from m5.objects.ReplacementPolicies import * 49from m5.objects.Tags import * 50 51 52# Enum for cache clusivity, currently mostly inclusive or mostly 53# exclusive. 54class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] --- 12 unchanged lines hidden (view full) --- 67 68 delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " 69 "MSHR with write requests to allow for " 70 "write coalescing") 71 72 block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 73 74 | 47from m5.objects.Prefetcher import BasePrefetcher 48from m5.objects.ReplacementPolicies import * 49from m5.objects.Tags import * 50 51 52# Enum for cache clusivity, currently mostly inclusive or mostly 53# exclusive. 54class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] --- 12 unchanged lines hidden (view full) --- 67 68 delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " 69 "MSHR with write requests to allow for " 70 "write coalescing") 71 72 block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 73 74 |
| 75class BaseCache(MemObject): | 75class BaseCache(ClockedObject): |
| 76 type = 'BaseCache' 77 abstract = True 78 cxx_header = "mem/cache/base.hh" 79 80 size = Param.MemorySize("Capacity") 81 assoc = Param.Unsigned("Associativity") 82 83 tag_latency = Param.Cycles("Tag lookup latency") --- 74 unchanged lines hidden --- | 76 type = 'BaseCache' 77 abstract = True 78 cxx_header = "mem/cache/base.hh" 79 80 size = Param.MemorySize("Capacity") 81 assoc = Param.Unsigned("Associativity") 82 83 tag_latency = Param.Cycles("Tag lookup latency") --- 74 unchanged lines hidden --- |