| Cache.py (12600:e670dd17c8cf) | Cache.py (12724:4f6fac3191d2) |
|---|---|
| 1# Copyright (c) 2012-2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41 42from m5.params import * 43from m5.proxy import * 44from MemObject import MemObject 45from Prefetcher import BasePrefetcher 46from ReplacementPolicies import * 47from Tags import * 48 | 1# Copyright (c) 2012-2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41 42from m5.params import * 43from m5.proxy import * 44from MemObject import MemObject 45from Prefetcher import BasePrefetcher 46from ReplacementPolicies import * 47from Tags import * 48 |
| 49 50# Enum for cache clusivity, currently mostly inclusive or mostly 51# exclusive. 52class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] 53 54 |
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| 49class BaseCache(MemObject): 50 type = 'BaseCache' 51 abstract = True 52 cxx_header = "mem/cache/base.hh" 53 54 size = Param.MemorySize("Capacity") 55 assoc = Param.Unsigned("Associativity") 56 --- 28 unchanged lines hidden (view full) --- 85 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 86 mem_side = MasterPort("Downstream port closer to memory") 87 88 addr_ranges = VectorParam.AddrRange([AllMemory], 89 "Address range for the CPU-side port (to allow striping)") 90 91 system = Param.System(Parent.any, "System we belong to") 92 | 55class BaseCache(MemObject): 56 type = 'BaseCache' 57 abstract = True 58 cxx_header = "mem/cache/base.hh" 59 60 size = Param.MemorySize("Capacity") 61 assoc = Param.Unsigned("Associativity") 62 --- 28 unchanged lines hidden (view full) --- 91 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 92 mem_side = MasterPort("Downstream port closer to memory") 93 94 addr_ranges = VectorParam.AddrRange([AllMemory], 95 "Address range for the CPU-side port (to allow striping)") 96 97 system = Param.System(Parent.any, "System we belong to") 98 |
| 93# Enum for cache clusivity, currently mostly inclusive or mostly 94# exclusive. 95class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] | 99 # Determine if this cache sends out writebacks for clean lines, or 100 # simply clean evicts. In cases where a downstream cache is mostly 101 # exclusive with respect to this cache (acting as a victim cache), 102 # the clean writebacks are essential for performance. In general 103 # this should be set to True for anything but the last-level 104 # cache. 105 writeback_clean = Param.Bool(False, "Writeback clean lines") |
| 96 | 106 |
| 97class Cache(BaseCache): 98 type = 'Cache' 99 cxx_header = 'mem/cache/cache.hh' 100 | |
| 101 # Control whether this cache should be mostly inclusive or mostly 102 # exclusive with respect to upstream caches. The behaviour on a 103 # fill is determined accordingly. For a mostly inclusive cache, 104 # blocks are allocated on all fill operations. Thus, L1 caches 105 # should be set as mostly inclusive even if they have no upstream 106 # caches. In the case of a mostly exclusive cache, fills are not 107 # allocating unless they came directly from a non-caching source, 108 # e.g. a table walker. Additionally, on a hit from an upstream 109 # cache a line is dropped for a mostly exclusive cache. 110 clusivity = Param.Clusivity('mostly_incl', 111 "Clusivity with upstream cache") 112 | 107 # Control whether this cache should be mostly inclusive or mostly 108 # exclusive with respect to upstream caches. The behaviour on a 109 # fill is determined accordingly. For a mostly inclusive cache, 110 # blocks are allocated on all fill operations. Thus, L1 caches 111 # should be set as mostly inclusive even if they have no upstream 112 # caches. In the case of a mostly exclusive cache, fills are not 113 # allocating unless they came directly from a non-caching source, 114 # e.g. a table walker. Additionally, on a hit from an upstream 115 # cache a line is dropped for a mostly exclusive cache. 116 clusivity = Param.Clusivity('mostly_incl', 117 "Clusivity with upstream cache") 118 |
| 113 # Determine if this cache sends out writebacks for clean lines, or 114 # simply clean evicts. In cases where a downstream cache is mostly 115 # exclusive with respect to this cache (acting as a victim cache), 116 # the clean writebacks are essential for performance. In general 117 # this should be set to True for anything but the last-level 118 # cache. 119 writeback_clean = Param.Bool(False, "Writeback clean lines") | 119 120class Cache(BaseCache): 121 type = 'Cache' 122 cxx_header = 'mem/cache/cache.hh' |