Cache.py (11053:62544e45c0f4) Cache.py (11197:f8fdd931e674)
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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79 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
80 mem_side = MasterPort("Downstream port closer to memory")
81
82 addr_ranges = VectorParam.AddrRange([AllMemory],
83 "Address range for the CPU-side port (to allow striping)")
84
85 system = Param.System(Parent.any, "System we belong to")
86
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 70 unchanged lines hidden (view full) ---

79 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
80 mem_side = MasterPort("Downstream port closer to memory")
81
82 addr_ranges = VectorParam.AddrRange([AllMemory],
83 "Address range for the CPU-side port (to allow striping)")
84
85 system = Param.System(Parent.any, "System we belong to")
86
87# Enum for cache clusivity, currently mostly inclusive or mostly
88# exclusive.
89class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
90
87class Cache(BaseCache):
88 type = 'Cache'
89 cxx_header = 'mem/cache/cache.hh'
91class Cache(BaseCache):
92 type = 'Cache'
93 cxx_header = 'mem/cache/cache.hh'
94
95 # Control whether this cache should be mostly inclusive or mostly
96 # exclusive with respect to upstream caches. The behaviour on a
97 # fill is determined accordingly. For a mostly inclusive cache,
98 # blocks are allocated on all fill operations. Thus, L1 caches
99 # should be set as mostly inclusive even if they have no upstream
100 # caches. In the case of a mostly exclusive cache, fills are not
101 # allocating unless they came directly from a non-caching source,
102 # e.g. a table walker. Additionally, on a hit from an upstream
103 # cache a line is dropped for a mostly exclusive cache.
104 clusivity = Param.Clusivity('mostly_incl',
105 "Clusivity with upstream cache")