1# Copyright (c) 2012-2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 29 unchanged lines hidden (view full) --- 38# 39# Authors: Nathan Binkert 40# Andreas Hansson 41 42from m5.params import * 43from m5.proxy import * 44from MemObject import MemObject 45from Prefetcher import BasePrefetcher |
46from ReplacementPolicies import * |
47from Tags import * 48 49class BaseCache(MemObject): 50 type = 'BaseCache' 51 abstract = True 52 cxx_header = "mem/cache/base.hh" 53 54 size = Param.MemorySize("Capacity") --- 15 unchanged lines hidden (view full) --- 70 write_buffers = Param.Unsigned(8, "Number of write buffers") 71 72 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 73 74 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 75 prefetch_on_access = Param.Bool(False, 76 "Notify the hardware prefetcher on every access (not just misses)") 77 |
78 tags = Param.BaseTags(BaseSetAssoc(), "Tag store") 79 replacement_policy = Param.BaseReplacementPolicy(LRURP(), 80 "Replacement policy") 81 |
82 sequential_access = Param.Bool(False, 83 "Whether to access tags and data sequentially") 84 85 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 86 mem_side = MasterPort("Downstream port closer to memory") 87 88 addr_ranges = VectorParam.AddrRange([AllMemory], 89 "Address range for the CPU-side port (to allow striping)") --- 30 unchanged lines hidden --- |