1# Copyright (c) 2012-2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 50 unchanged lines hidden (view full) --- 59 max_miss_count = Param.Counter(0, 60 "Number of misses to handle before calling exit") 61 62 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 63 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 64 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 65 write_buffers = Param.Unsigned(8, "Number of write buffers") 66 |
67 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 68 69 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 70 prefetch_on_access = Param.Bool(False, 71 "Notify the hardware prefetcher on every access (not just misses)") 72 73 tags = Param.BaseTags(LRU(), "Tag store (replacement policy)") 74 sequential_access = Param.Bool(False, --- 37 unchanged lines hidden --- |