1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.params import *
43from m5.proxy import *
44from MemObject import MemObject
45from Prefetcher import BasePrefetcher
46from ReplacementPolicies import *
47from Tags import *
48
| 1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.params import *
43from m5.proxy import *
44from MemObject import MemObject
45from Prefetcher import BasePrefetcher
46from ReplacementPolicies import *
47from Tags import *
48
|
| 49
50# Enum for cache clusivity, currently mostly inclusive or mostly
51# exclusive.
52class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
53
54
|
49class BaseCache(MemObject):
50 type = 'BaseCache'
51 abstract = True
52 cxx_header = "mem/cache/base.hh"
53
54 size = Param.MemorySize("Capacity")
55 assoc = Param.Unsigned("Associativity")
56
57 tag_latency = Param.Cycles("Tag lookup latency")
58 data_latency = Param.Cycles("Data access latency")
59 response_latency = Param.Cycles("Latency for the return path on a miss");
60
61 warmup_percentage = Param.Percent(0,
62 "Percentage of tags to be touched to warm up the cache")
63
64 max_miss_count = Param.Counter(0,
65 "Number of misses to handle before calling exit")
66
67 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
68 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
69 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
70 write_buffers = Param.Unsigned(8, "Number of write buffers")
71
72 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
73
74 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
75 prefetch_on_access = Param.Bool(False,
76 "Notify the hardware prefetcher on every access (not just misses)")
77
78 tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
79 replacement_policy = Param.BaseReplacementPolicy(LRURP(),
80 "Replacement policy")
81
82 sequential_access = Param.Bool(False,
83 "Whether to access tags and data sequentially")
84
85 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
86 mem_side = MasterPort("Downstream port closer to memory")
87
88 addr_ranges = VectorParam.AddrRange([AllMemory],
89 "Address range for the CPU-side port (to allow striping)")
90
91 system = Param.System(Parent.any, "System we belong to")
92
| 55class BaseCache(MemObject):
56 type = 'BaseCache'
57 abstract = True
58 cxx_header = "mem/cache/base.hh"
59
60 size = Param.MemorySize("Capacity")
61 assoc = Param.Unsigned("Associativity")
62
63 tag_latency = Param.Cycles("Tag lookup latency")
64 data_latency = Param.Cycles("Data access latency")
65 response_latency = Param.Cycles("Latency for the return path on a miss");
66
67 warmup_percentage = Param.Percent(0,
68 "Percentage of tags to be touched to warm up the cache")
69
70 max_miss_count = Param.Counter(0,
71 "Number of misses to handle before calling exit")
72
73 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
74 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
75 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
76 write_buffers = Param.Unsigned(8, "Number of write buffers")
77
78 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
79
80 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
81 prefetch_on_access = Param.Bool(False,
82 "Notify the hardware prefetcher on every access (not just misses)")
83
84 tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
85 replacement_policy = Param.BaseReplacementPolicy(LRURP(),
86 "Replacement policy")
87
88 sequential_access = Param.Bool(False,
89 "Whether to access tags and data sequentially")
90
91 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
92 mem_side = MasterPort("Downstream port closer to memory")
93
94 addr_ranges = VectorParam.AddrRange([AllMemory],
95 "Address range for the CPU-side port (to allow striping)")
96
97 system = Param.System(Parent.any, "System we belong to")
98
|
93# Enum for cache clusivity, currently mostly inclusive or mostly
94# exclusive.
95class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
| 99 # Determine if this cache sends out writebacks for clean lines, or
100 # simply clean evicts. In cases where a downstream cache is mostly
101 # exclusive with respect to this cache (acting as a victim cache),
102 # the clean writebacks are essential for performance. In general
103 # this should be set to True for anything but the last-level
104 # cache.
105 writeback_clean = Param.Bool(False, "Writeback clean lines")
|
96
| 106
|
97class Cache(BaseCache):
98 type = 'Cache'
99 cxx_header = 'mem/cache/cache.hh'
100
| |
101 # Control whether this cache should be mostly inclusive or mostly
102 # exclusive with respect to upstream caches. The behaviour on a
103 # fill is determined accordingly. For a mostly inclusive cache,
104 # blocks are allocated on all fill operations. Thus, L1 caches
105 # should be set as mostly inclusive even if they have no upstream
106 # caches. In the case of a mostly exclusive cache, fills are not
107 # allocating unless they came directly from a non-caching source,
108 # e.g. a table walker. Additionally, on a hit from an upstream
109 # cache a line is dropped for a mostly exclusive cache.
110 clusivity = Param.Clusivity('mostly_incl',
111 "Clusivity with upstream cache")
112
| 107 # Control whether this cache should be mostly inclusive or mostly
108 # exclusive with respect to upstream caches. The behaviour on a
109 # fill is determined accordingly. For a mostly inclusive cache,
110 # blocks are allocated on all fill operations. Thus, L1 caches
111 # should be set as mostly inclusive even if they have no upstream
112 # caches. In the case of a mostly exclusive cache, fills are not
113 # allocating unless they came directly from a non-caching source,
114 # e.g. a table walker. Additionally, on a hit from an upstream
115 # cache a line is dropped for a mostly exclusive cache.
116 clusivity = Param.Clusivity('mostly_incl',
117 "Clusivity with upstream cache")
118
|
113 # Determine if this cache sends out writebacks for clean lines, or
114 # simply clean evicts. In cases where a downstream cache is mostly
115 # exclusive with respect to this cache (acting as a victim cache),
116 # the clean writebacks are essential for performance. In general
117 # this should be set to True for anything but the last-level
118 # cache.
119 writeback_clean = Param.Bool(False, "Writeback clean lines")
| 119
120class Cache(BaseCache):
121 type = 'Cache'
122 cxx_header = 'mem/cache/cache.hh'
|
| |