1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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79 cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
80 mem_side = MasterPort("Downstream port closer to memory")
81
82 addr_ranges = VectorParam.AddrRange([AllMemory],
83 "Address range for the CPU-side port (to allow striping)")
84
85 system = Param.System(Parent.any, "System we belong to")
86
87class Cache(BaseCache):
88 type = 'Cache'
89 cxx_header = 'mem/cache/cache.hh'