bridge.cc (11334:9bd2e84abdca) bridge.cc (11793:ef606668d247)
1/*
2 * Copyright (c) 2011-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43 */
44
45/**
46 * @file
47 * Implementation of a memory-mapped bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
1/*
2 * Copyright (c) 2011-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 34 unchanged lines hidden (view full) ---

43 */
44
45/**
46 * @file
47 * Implementation of a memory-mapped bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#include "mem/bridge.hh"
52
51#include "base/trace.hh"
52#include "debug/Bridge.hh"
53#include "base/trace.hh"
54#include "debug/Bridge.hh"
53#include "mem/bridge.hh"
54#include "params/Bridge.hh"
55
56Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
57 Bridge& _bridge,
58 BridgeMasterPort& _masterPort,
59 Cycles _delay, int _resp_limit,
60 std::vector<AddrRange> _ranges)
61 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),

--- 345 unchanged lines hidden --- 		55#include "params/Bridge.hh"
56
57Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
58 Bridge& _bridge,
59 BridgeMasterPort& _masterPort,
60 Cycles _delay, int _resp_limit,
61 std::vector<AddrRange> _ranges)
62 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),

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