1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 65 unchanged lines hidden (view full) --- 74 : MasterPort(_name, _bridge), bridge(_bridge), slavePort(_slavePort), 75 delay(_delay), inRetry(false), reqQueueLimit(_req_limit), 76 sendEvent(*this) 77{ 78} 79 80Bridge::Bridge(Params *p) 81 : MemObject(p), |
82 slavePort(p->name + ".slave", this, masterPort, p->delay, |
83 p->nack_delay, p->resp_size, p->ranges), |
84 masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size), |
85 ackWrites(p->write_ack), _params(p) 86{ 87 if (ackWrites) 88 panic("No support for acknowledging writes\n"); 89} 90 91MasterPort& 92Bridge::getMasterPort(const std::string &if_name, int idx) --- 363 unchanged lines hidden --- |