1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Steve Reinhardt
42 * Andreas Hansson
43 */
44
45/**
46 * @file
47 * Implementation of a memory-mapped bus bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#include "base/trace.hh"
52#include "debug/Bridge.hh"
53#include "mem/bridge.hh"
54#include "params/Bridge.hh"
55
56Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
57 Bridge& _bridge,
58 BridgeMasterPort& _masterPort,
59 Cycles _delay, int _resp_limit,
60 std::vector<AddrRange> _ranges)
61 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
62 delay(_delay), ranges(_ranges.begin(), _ranges.end()),
63 outstandingResponses(0), retryReq(false),
64 respQueueLimit(_resp_limit), sendEvent(*this)
65{
66}
67
68Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
69 Bridge& _bridge,
70 BridgeSlavePort& _slavePort,
71 Cycles _delay, int _req_limit)
72 : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
73 delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
74{
75}
76
77Bridge::Bridge(Params *p)
78 : MemObject(p),
79 slavePort(p->name + ".slave", *this, masterPort,
80 ticksToCycles(p->delay), p->resp_size, p->ranges),
81 masterPort(p->name + ".master", *this, slavePort,
82 ticksToCycles(p->delay), p->req_size)
83{
84}
85
86BaseMasterPort&
87Bridge::getMasterPort(const std::string &if_name, PortID idx)
88{
89 if (if_name == "master")
90 return masterPort;
91 else
92 // pass it along to our super class
93 return MemObject::getMasterPort(if_name, idx);
94}
95
96BaseSlavePort&
97Bridge::getSlavePort(const std::string &if_name, PortID idx)
98{
99 if (if_name == "slave")
100 return slavePort;
101 else
102 // pass it along to our super class
103 return MemObject::getSlavePort(if_name, idx);
104}
105
106void
107Bridge::init()
108{
109 // make sure both sides are connected and have the same block size
110 if (!slavePort.isConnected() || !masterPort.isConnected())
111 fatal("Both ports of bus bridge are not connected to a bus.\n");
112
113 if (slavePort.peerBlockSize() != masterPort.peerBlockSize())
114 fatal("Slave port size %d, master port size %d \n " \
115 "Busses don't have the same block size... Not supported.\n",
116 slavePort.peerBlockSize(), masterPort.peerBlockSize());
117
118 // notify the master side of our address ranges
119 slavePort.sendRangeChange();
120}
121
122bool
123Bridge::BridgeSlavePort::respQueueFull()
124{
125 return outstandingResponses == respQueueLimit;
126}
127
128bool
129Bridge::BridgeMasterPort::reqQueueFull()
130{
131 return transmitList.size() == reqQueueLimit;
132}
133
134bool
135Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
136{
137 // all checks are done when the request is accepted on the slave
138 // side, so we are guaranteed to have space for the response
139 DPRINTF(Bridge, "recvTimingResp: %s addr 0x%x\n",
140 pkt->cmdString(), pkt->getAddr());
141
142 DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
143
144 // @todo: We need to pay for this and not just zero it out
145 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
146
147 slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
148
149 return true;
150}
151
152bool
153Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
154{
155 DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
156 pkt->cmdString(), pkt->getAddr());
157
158 // ensure we do not have something waiting to retry
159 if(retryReq)
160 return false;
161
162 DPRINTF(Bridge, "Response queue size: %d outresp: %d\n",
163 transmitList.size(), outstandingResponses);
164
165 if (masterPort.reqQueueFull()) {
166 DPRINTF(Bridge, "Request queue full\n");
167 retryReq = true;
168 } else if (pkt->needsResponse()) {
169 if (respQueueFull()) {
170 DPRINTF(Bridge, "Response queue full\n");
171 retryReq = true;
172 } else {
173 DPRINTF(Bridge, "Reserving space for response\n");
174 assert(outstandingResponses != respQueueLimit);
175 ++outstandingResponses;
176 retryReq = false;
177
178 // @todo: We need to pay for this and not just zero it out
179 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
180
181 masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
182 }
183 }
184
185 // remember that we are now stalling a packet and that we have to
186 // tell the sending master to retry once space becomes available,
187 // we make no distinction whether the stalling is due to the
188 // request queue or response queue being full
189 return !retryReq;
190}
191
192void
193Bridge::BridgeSlavePort::retryStalledReq()
194{
195 if (retryReq) {
196 DPRINTF(Bridge, "Request waiting for retry, now retrying\n");
197 retryReq = false;
198 sendRetry();
199 }
200}
201
202void
203Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
204{
205 // If we expect to see a response, we need to restore the source
206 // and destination field that is potentially changed by a second
207 // bus
208 if (!pkt->memInhibitAsserted() && pkt->needsResponse()) {
209 // Update the sender state so we can deal with the response
210 // appropriately
211 pkt->pushSenderState(new RequestState(pkt->getSrc()));
212 }
213
214 // If we're about to put this packet at the head of the queue, we
215 // need to schedule an event to do the transmit. Otherwise there
216 // should already be an event scheduled for sending the head
217 // packet.
218 if (transmitList.empty()) {
219 bridge.schedule(sendEvent, when);
220 }
221
222 assert(transmitList.size() != reqQueueLimit);
223
224 transmitList.push_back(DeferredPacket(pkt, when));
225}
226
227
228void
229Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
230{
231 // This is a response for a request we forwarded earlier. The
232 // corresponding request state should be stored in the packet's
233 // senderState field.
234 RequestState *req_state =
235 dynamic_cast<RequestState*>(pkt->popSenderState());
236 assert(req_state != NULL);
237 pkt->setDest(req_state->origSrc);
238 delete req_state;
239
240 // the bridge assumes that at least one bus has set the
241 // destination field of the packet
242 assert(pkt->isDestValid());
243 DPRINTF(Bridge, "response, new dest %d\n", pkt->getDest());
244
245 // If we're about to put this packet at the head of the queue, we
246 // need to schedule an event to do the transmit. Otherwise there
247 // should already be an event scheduled for sending the head
248 // packet.
249 if (transmitList.empty()) {
250 bridge.schedule(sendEvent, when);
251 }
252
253 transmitList.push_back(DeferredPacket(pkt, when));
254}
255
256void
257Bridge::BridgeMasterPort::trySendTiming()
258{
259 assert(!transmitList.empty());
260
261 DeferredPacket req = transmitList.front();
262
263 assert(req.tick <= curTick());
264
265 PacketPtr pkt = req.pkt;
266
267 DPRINTF(Bridge, "trySend request addr 0x%x, queue size %d\n",
268 pkt->getAddr(), transmitList.size());
269
270 if (sendTimingReq(pkt)) {
271 // send successful
272 transmitList.pop_front();
273 DPRINTF(Bridge, "trySend request successful\n");
274
275 // If there are more packets to send, schedule event to try again.
276 if (!transmitList.empty()) {
277 req = transmitList.front();
278 DPRINTF(Bridge, "Scheduling next send\n");
279 bridge.schedule(sendEvent, std::max(req.tick,
| 1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Steve Reinhardt
42 * Andreas Hansson
43 */
44
45/**
46 * @file
47 * Implementation of a memory-mapped bus bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#include "base/trace.hh"
52#include "debug/Bridge.hh"
53#include "mem/bridge.hh"
54#include "params/Bridge.hh"
55
56Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
57 Bridge& _bridge,
58 BridgeMasterPort& _masterPort,
59 Cycles _delay, int _resp_limit,
60 std::vector<AddrRange> _ranges)
61 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
62 delay(_delay), ranges(_ranges.begin(), _ranges.end()),
63 outstandingResponses(0), retryReq(false),
64 respQueueLimit(_resp_limit), sendEvent(*this)
65{
66}
67
68Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
69 Bridge& _bridge,
70 BridgeSlavePort& _slavePort,
71 Cycles _delay, int _req_limit)
72 : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
73 delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
74{
75}
76
77Bridge::Bridge(Params *p)
78 : MemObject(p),
79 slavePort(p->name + ".slave", *this, masterPort,
80 ticksToCycles(p->delay), p->resp_size, p->ranges),
81 masterPort(p->name + ".master", *this, slavePort,
82 ticksToCycles(p->delay), p->req_size)
83{
84}
85
86BaseMasterPort&
87Bridge::getMasterPort(const std::string &if_name, PortID idx)
88{
89 if (if_name == "master")
90 return masterPort;
91 else
92 // pass it along to our super class
93 return MemObject::getMasterPort(if_name, idx);
94}
95
96BaseSlavePort&
97Bridge::getSlavePort(const std::string &if_name, PortID idx)
98{
99 if (if_name == "slave")
100 return slavePort;
101 else
102 // pass it along to our super class
103 return MemObject::getSlavePort(if_name, idx);
104}
105
106void
107Bridge::init()
108{
109 // make sure both sides are connected and have the same block size
110 if (!slavePort.isConnected() || !masterPort.isConnected())
111 fatal("Both ports of bus bridge are not connected to a bus.\n");
112
113 if (slavePort.peerBlockSize() != masterPort.peerBlockSize())
114 fatal("Slave port size %d, master port size %d \n " \
115 "Busses don't have the same block size... Not supported.\n",
116 slavePort.peerBlockSize(), masterPort.peerBlockSize());
117
118 // notify the master side of our address ranges
119 slavePort.sendRangeChange();
120}
121
122bool
123Bridge::BridgeSlavePort::respQueueFull()
124{
125 return outstandingResponses == respQueueLimit;
126}
127
128bool
129Bridge::BridgeMasterPort::reqQueueFull()
130{
131 return transmitList.size() == reqQueueLimit;
132}
133
134bool
135Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
136{
137 // all checks are done when the request is accepted on the slave
138 // side, so we are guaranteed to have space for the response
139 DPRINTF(Bridge, "recvTimingResp: %s addr 0x%x\n",
140 pkt->cmdString(), pkt->getAddr());
141
142 DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
143
144 // @todo: We need to pay for this and not just zero it out
145 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
146
147 slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
148
149 return true;
150}
151
152bool
153Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
154{
155 DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
156 pkt->cmdString(), pkt->getAddr());
157
158 // ensure we do not have something waiting to retry
159 if(retryReq)
160 return false;
161
162 DPRINTF(Bridge, "Response queue size: %d outresp: %d\n",
163 transmitList.size(), outstandingResponses);
164
165 if (masterPort.reqQueueFull()) {
166 DPRINTF(Bridge, "Request queue full\n");
167 retryReq = true;
168 } else if (pkt->needsResponse()) {
169 if (respQueueFull()) {
170 DPRINTF(Bridge, "Response queue full\n");
171 retryReq = true;
172 } else {
173 DPRINTF(Bridge, "Reserving space for response\n");
174 assert(outstandingResponses != respQueueLimit);
175 ++outstandingResponses;
176 retryReq = false;
177
178 // @todo: We need to pay for this and not just zero it out
179 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
180
181 masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
182 }
183 }
184
185 // remember that we are now stalling a packet and that we have to
186 // tell the sending master to retry once space becomes available,
187 // we make no distinction whether the stalling is due to the
188 // request queue or response queue being full
189 return !retryReq;
190}
191
192void
193Bridge::BridgeSlavePort::retryStalledReq()
194{
195 if (retryReq) {
196 DPRINTF(Bridge, "Request waiting for retry, now retrying\n");
197 retryReq = false;
198 sendRetry();
199 }
200}
201
202void
203Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
204{
205 // If we expect to see a response, we need to restore the source
206 // and destination field that is potentially changed by a second
207 // bus
208 if (!pkt->memInhibitAsserted() && pkt->needsResponse()) {
209 // Update the sender state so we can deal with the response
210 // appropriately
211 pkt->pushSenderState(new RequestState(pkt->getSrc()));
212 }
213
214 // If we're about to put this packet at the head of the queue, we
215 // need to schedule an event to do the transmit. Otherwise there
216 // should already be an event scheduled for sending the head
217 // packet.
218 if (transmitList.empty()) {
219 bridge.schedule(sendEvent, when);
220 }
221
222 assert(transmitList.size() != reqQueueLimit);
223
224 transmitList.push_back(DeferredPacket(pkt, when));
225}
226
227
228void
229Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
230{
231 // This is a response for a request we forwarded earlier. The
232 // corresponding request state should be stored in the packet's
233 // senderState field.
234 RequestState *req_state =
235 dynamic_cast<RequestState*>(pkt->popSenderState());
236 assert(req_state != NULL);
237 pkt->setDest(req_state->origSrc);
238 delete req_state;
239
240 // the bridge assumes that at least one bus has set the
241 // destination field of the packet
242 assert(pkt->isDestValid());
243 DPRINTF(Bridge, "response, new dest %d\n", pkt->getDest());
244
245 // If we're about to put this packet at the head of the queue, we
246 // need to schedule an event to do the transmit. Otherwise there
247 // should already be an event scheduled for sending the head
248 // packet.
249 if (transmitList.empty()) {
250 bridge.schedule(sendEvent, when);
251 }
252
253 transmitList.push_back(DeferredPacket(pkt, when));
254}
255
256void
257Bridge::BridgeMasterPort::trySendTiming()
258{
259 assert(!transmitList.empty());
260
261 DeferredPacket req = transmitList.front();
262
263 assert(req.tick <= curTick());
264
265 PacketPtr pkt = req.pkt;
266
267 DPRINTF(Bridge, "trySend request addr 0x%x, queue size %d\n",
268 pkt->getAddr(), transmitList.size());
269
270 if (sendTimingReq(pkt)) {
271 // send successful
272 transmitList.pop_front();
273 DPRINTF(Bridge, "trySend request successful\n");
274
275 // If there are more packets to send, schedule event to try again.
276 if (!transmitList.empty()) {
277 req = transmitList.front();
278 DPRINTF(Bridge, "Scheduling next send\n");
279 bridge.schedule(sendEvent, std::max(req.tick,
|