1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * AbstractMemory declaration
47 */
48
49#ifndef __ABSTRACT_MEMORY_HH__
50#define __ABSTRACT_MEMORY_HH__
51
52#include "mem/mem_object.hh"
53#include "params/AbstractMemory.hh"
54#include "sim/stats.hh"
55
56
57class System;
58
59/**
60 * Locked address class that represents a physical address and a
61 * context id.
62 */
63class LockedAddr {
64
65 private:
66
67 // on alpha, minimum LL/SC granularity is 16 bytes, so lower
68 // bits need to masked off.
69 static const Addr Addr_Mask = 0xf;
70
71 public:
72
73 // locked address
74 Addr addr;
75
76 // locking hw context
77 const ContextID contextId;
78
79 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
80
81 // check for matching execution context
82 bool matchesContext(Request *req) const
83 {
84 return (contextId == req->contextId());
85 }
86
87 LockedAddr(Request *req) : addr(mask(req->getPaddr())),
88 contextId(req->contextId())
89 {}
90
91 // constructor for unserialization use
92 LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid)
93 {}
94};
95
96/**
97 * An abstract memory represents a contiguous block of physical
98 * memory, with an associated address range, and also provides basic
99 * functionality for reading and writing this memory without any
100 * timing information. It is a MemObject since any subclass must have
101 * at least one slave port.
102 */
103class AbstractMemory : public MemObject
104{
105 protected:
106
107 // Address range of this memory
108 AddrRange range;
109
110 // Pointer to host memory used to implement this memory
111 uint8_t* pmemAddr;
112
113 // Enable specific memories to be reported to the configuration table
114 bool confTableReported;
115
116 // Should the memory appear in the global address map
117 bool inAddrMap;
118
119 std::list<LockedAddr> lockedAddrList;
120
121 // helper function for checkLockedAddrs(): we really want to
122 // inline a quick check for an empty locked addr list (hopefully
123 // the common case), and do the full list search (if necessary) in
124 // this out-of-line function
125 bool checkLockedAddrList(PacketPtr pkt);
126
127 // Record the address of a load-locked operation so that we can
128 // clear the execution context's lock flag if a matching store is
129 // performed
130 void trackLoadLocked(PacketPtr pkt);
131
132 // Compare a store address with any locked addresses so we can
133 // clear the lock flag appropriately. Return value set to 'false'
134 // if store operation should be suppressed (because it was a
135 // conditional store and the address was no longer locked by the
136 // requesting execution context), 'true' otherwise. Note that
137 // this method must be called on *all* stores since even
138 // non-conditional stores must clear any matching lock addresses.
139 bool writeOK(PacketPtr pkt) {
140 Request *req = pkt->req;
141 if (lockedAddrList.empty()) {
142 // no locked addrs: nothing to check, store_conditional fails
143 bool isLLSC = pkt->isLLSC();
144 if (isLLSC) {
145 req->setExtraData(0);
146 }
147 return !isLLSC; // only do write if not an sc
148 } else {
149 // iterate over list...
150 return checkLockedAddrList(pkt);
151 }
152 }
153
154 /** Number of total bytes read from this memory */
155 Stats::Vector bytesRead;
156 /** Number of instruction bytes read from this memory */
157 Stats::Vector bytesInstRead;
158 /** Number of bytes written to this memory */
159 Stats::Vector bytesWritten;
160 /** Number of read requests */
161 Stats::Vector numReads;
162 /** Number of write requests */
163 Stats::Vector numWrites;
164 /** Number of other requests */
165 Stats::Vector numOther;
166 /** Read bandwidth from this memory */
167 Stats::Formula bwRead;
168 /** Read bandwidth from this memory */
169 Stats::Formula bwInstRead;
170 /** Write bandwidth from this memory */
171 Stats::Formula bwWrite;
172 /** Total bandwidth from this memory */
173 Stats::Formula bwTotal;
174
175 /** Pointor to the System object.
176 * This is used for getting the number of masters in the system which is
177 * needed when registering stats
178 */
179 System *_system;
180
181
182 private:
183
184 // Prevent copying
185 AbstractMemory(const AbstractMemory&);
186
187 // Prevent assignment
188 AbstractMemory& operator=(const AbstractMemory&);
189
190 public:
191
192 typedef AbstractMemoryParams Params;
193
194 AbstractMemory(const Params* p);
195 virtual ~AbstractMemory() {}
196
197 /**
198 * Initialise this memory.
199 */
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * AbstractMemory declaration
47 */
48
49#ifndef __ABSTRACT_MEMORY_HH__
50#define __ABSTRACT_MEMORY_HH__
51
52#include "mem/mem_object.hh"
53#include "params/AbstractMemory.hh"
54#include "sim/stats.hh"
55
56
57class System;
58
59/**
60 * Locked address class that represents a physical address and a
61 * context id.
62 */
63class LockedAddr {
64
65 private:
66
67 // on alpha, minimum LL/SC granularity is 16 bytes, so lower
68 // bits need to masked off.
69 static const Addr Addr_Mask = 0xf;
70
71 public:
72
73 // locked address
74 Addr addr;
75
76 // locking hw context
77 const ContextID contextId;
78
79 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
80
81 // check for matching execution context
82 bool matchesContext(Request *req) const
83 {
84 return (contextId == req->contextId());
85 }
86
87 LockedAddr(Request *req) : addr(mask(req->getPaddr())),
88 contextId(req->contextId())
89 {}
90
91 // constructor for unserialization use
92 LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid)
93 {}
94};
95
96/**
97 * An abstract memory represents a contiguous block of physical
98 * memory, with an associated address range, and also provides basic
99 * functionality for reading and writing this memory without any
100 * timing information. It is a MemObject since any subclass must have
101 * at least one slave port.
102 */
103class AbstractMemory : public MemObject
104{
105 protected:
106
107 // Address range of this memory
108 AddrRange range;
109
110 // Pointer to host memory used to implement this memory
111 uint8_t* pmemAddr;
112
113 // Enable specific memories to be reported to the configuration table
114 bool confTableReported;
115
116 // Should the memory appear in the global address map
117 bool inAddrMap;
118
119 std::list<LockedAddr> lockedAddrList;
120
121 // helper function for checkLockedAddrs(): we really want to
122 // inline a quick check for an empty locked addr list (hopefully
123 // the common case), and do the full list search (if necessary) in
124 // this out-of-line function
125 bool checkLockedAddrList(PacketPtr pkt);
126
127 // Record the address of a load-locked operation so that we can
128 // clear the execution context's lock flag if a matching store is
129 // performed
130 void trackLoadLocked(PacketPtr pkt);
131
132 // Compare a store address with any locked addresses so we can
133 // clear the lock flag appropriately. Return value set to 'false'
134 // if store operation should be suppressed (because it was a
135 // conditional store and the address was no longer locked by the
136 // requesting execution context), 'true' otherwise. Note that
137 // this method must be called on *all* stores since even
138 // non-conditional stores must clear any matching lock addresses.
139 bool writeOK(PacketPtr pkt) {
140 Request *req = pkt->req;
141 if (lockedAddrList.empty()) {
142 // no locked addrs: nothing to check, store_conditional fails
143 bool isLLSC = pkt->isLLSC();
144 if (isLLSC) {
145 req->setExtraData(0);
146 }
147 return !isLLSC; // only do write if not an sc
148 } else {
149 // iterate over list...
150 return checkLockedAddrList(pkt);
151 }
152 }
153
154 /** Number of total bytes read from this memory */
155 Stats::Vector bytesRead;
156 /** Number of instruction bytes read from this memory */
157 Stats::Vector bytesInstRead;
158 /** Number of bytes written to this memory */
159 Stats::Vector bytesWritten;
160 /** Number of read requests */
161 Stats::Vector numReads;
162 /** Number of write requests */
163 Stats::Vector numWrites;
164 /** Number of other requests */
165 Stats::Vector numOther;
166 /** Read bandwidth from this memory */
167 Stats::Formula bwRead;
168 /** Read bandwidth from this memory */
169 Stats::Formula bwInstRead;
170 /** Write bandwidth from this memory */
171 Stats::Formula bwWrite;
172 /** Total bandwidth from this memory */
173 Stats::Formula bwTotal;
174
175 /** Pointor to the System object.
176 * This is used for getting the number of masters in the system which is
177 * needed when registering stats
178 */
179 System *_system;
180
181
182 private:
183
184 // Prevent copying
185 AbstractMemory(const AbstractMemory&);
186
187 // Prevent assignment
188 AbstractMemory& operator=(const AbstractMemory&);
189
190 public:
191
192 typedef AbstractMemoryParams Params;
193
194 AbstractMemory(const Params* p);
195 virtual ~AbstractMemory() {}
196
197 /**
198 * Initialise this memory.
199 */
|