abstract_mem.cc (12218:8c5db15dc8e7) abstract_mem.cc (12354:f7c29d65a656)
1/*
2 * Copyright (c) 2010-2012,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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394 }
395 if (pmemAddr)
396 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
397 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
398 numReads[pkt->req->masterId()]++;
399 bytesRead[pkt->req->masterId()] += pkt->getSize();
400 if (pkt->req->isInstFetch())
401 bytesInstRead[pkt->req->masterId()] += pkt->getSize();
1/*
2 * Copyright (c) 2010-2012,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 385 unchanged lines hidden (view full) ---

394 }
395 if (pmemAddr)
396 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
397 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
398 numReads[pkt->req->masterId()]++;
399 bytesRead[pkt->req->masterId()] += pkt->getSize();
400 if (pkt->req->isInstFetch())
401 bytesInstRead[pkt->req->masterId()] += pkt->getSize();
402 } else if (pkt->isInvalidate()) {
402 } else if (pkt->isInvalidate() || pkt->isClean()) {
403 assert(!pkt->isWrite());
404 // in a fastmem system invalidating and/or cleaning packets
405 // can be seen due to cache maintenance requests
406
403 // no need to do anything
407 // no need to do anything
404 // this clause is intentionally before the write clause: the only
405 // transaction that is both a write and an invalidate is
406 // WriteInvalidate, and for the sake of consistency, it does not
407 // write to memory. in a cacheless system, there are no WriteInv's
408 // because the Write -> WriteInvalidate rewrite happens in the cache.
409 } else if (pkt->isWrite()) {
410 if (writeOK(pkt)) {
411 if (pmemAddr) {
412 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
413 DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n",
414 __func__, pkt->getSize(), pkt->getAddr());
415 }
416 assert(!pkt->req->isInstFetch());
417 TRACE_PACKET("Write");
418 numWrites[pkt->req->masterId()]++;
419 bytesWritten[pkt->req->masterId()] += pkt->getSize();
420 }
421 } else {
408 } else if (pkt->isWrite()) {
409 if (writeOK(pkt)) {
410 if (pmemAddr) {
411 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
412 DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n",
413 __func__, pkt->getSize(), pkt->getAddr());
414 }
415 assert(!pkt->req->isInstFetch());
416 TRACE_PACKET("Write");
417 numWrites[pkt->req->masterId()]++;
418 bytesWritten[pkt->req->masterId()] += pkt->getSize();
419 }
420 } else {
422 panic("unimplemented");
421 panic("Unexpected packet %s", pkt->print());
423 }
424
425 if (pkt->needsResponse()) {
426 pkt->makeResponse();
427 }
428}
429
430void

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423
424 if (pkt->needsResponse()) {
425 pkt->makeResponse();
426 }
427}
428
429void

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