abstract_mem.cc (10563:755b18321206) abstract_mem.cc (10583:d1e1e8588881)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 365 unchanged lines hidden (view full) ---

374 }
375 if (pmemAddr)
376 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
377 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
378 numReads[pkt->req->masterId()]++;
379 bytesRead[pkt->req->masterId()] += pkt->getSize();
380 if (pkt->req->isInstFetch())
381 bytesInstRead[pkt->req->masterId()] += pkt->getSize();
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 365 unchanged lines hidden (view full) ---

374 }
375 if (pmemAddr)
376 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
377 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
378 numReads[pkt->req->masterId()]++;
379 bytesRead[pkt->req->masterId()] += pkt->getSize();
380 if (pkt->req->isInstFetch())
381 bytesInstRead[pkt->req->masterId()] += pkt->getSize();
382 } else if (pkt->isInvalidate()) {
383 // no need to do anything
384 // this clause is intentionally before the write clause: the only
385 // transaction that is both a write and an invalidate is
386 // WriteInvalidate, and for the sake of consistency, it does not
387 // write to memory. in a cacheless system, there are no WriteInv's
388 // because the Write -> WriteInvalidate rewrite happens in the cache.
382 } else if (pkt->isWrite()) {
383 if (writeOK(pkt)) {
384 if (pmemAddr) {
385 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
386 DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
387 __func__, pkt->getSize(), pkt->getAddr());
388 }
389 assert(!pkt->req->isInstFetch());
390 TRACE_PACKET("Write");
391 numWrites[pkt->req->masterId()]++;
392 bytesWritten[pkt->req->masterId()] += pkt->getSize();
393 }
389 } else if (pkt->isWrite()) {
390 if (writeOK(pkt)) {
391 if (pmemAddr) {
392 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
393 DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
394 __func__, pkt->getSize(), pkt->getAddr());
395 }
396 assert(!pkt->req->isInstFetch());
397 TRACE_PACKET("Write");
398 numWrites[pkt->req->masterId()]++;
399 bytesWritten[pkt->req->masterId()] += pkt->getSize();
400 }
394 } else if (pkt->isInvalidate()) {
395 // no need to do anything
396 } else {
397 panic("unimplemented");
398 }
399
400 if (pkt->needsResponse()) {
401 pkt->makeResponse();
402 }
403}

--- 33 unchanged lines hidden --- 		401 } else {
402 panic("unimplemented");
403 }
404
405 if (pkt->needsResponse()) {
406 pkt->makeResponse();
407 }
408}

--- 33 unchanged lines hidden ---