abstract_mem.cc (10102:b5de69974a2e) abstract_mem.cc (10466:73b7549d979e)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
45#include <vector>
46
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/LLSC.hh"
50#include "debug/MemoryAccess.hh"
51#include "mem/abstract_mem.hh"
52#include "mem/packet_access.hh"
53#include "sim/system.hh"
54
55using namespace std;
56
57AbstractMemory::AbstractMemory(const Params *p) :
58 MemObject(p), range(params()->range), pmemAddr(NULL),
59 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
60 _system(NULL)
61{
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/LLSC.hh"
50#include "debug/MemoryAccess.hh"
51#include "mem/abstract_mem.hh"
52#include "mem/packet_access.hh"
53#include "sim/system.hh"
54
55using namespace std;
56
57AbstractMemory::AbstractMemory(const Params *p) :
58 MemObject(p), range(params()->range), pmemAddr(NULL),
59 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
60 _system(NULL)
61{
62 if (size() % TheISA::PageBytes != 0)
62}
63
64void
65AbstractMemory::init()
66{
67 assert(system());
68
69 if (size() % _system->getPageBytes() != 0)
63 panic("Memory Size not divisible by page size\n");
64}
65
66void
67AbstractMemory::setBackingStore(uint8_t* pmem_addr)
68{
69 pmemAddr = pmem_addr;
70}

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322 DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
323 pkt->getAddr());
324 return;
325 }
326
327 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
328
329 if (pkt->cmd == MemCmd::SwapReq) {
70 panic("Memory Size not divisible by page size\n");
71}
72
73void
74AbstractMemory::setBackingStore(uint8_t* pmem_addr)
75{
76 pmemAddr = pmem_addr;
77}

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329 DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
330 pkt->getAddr());
331 return;
332 }
333
334 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
335
336 if (pkt->cmd == MemCmd::SwapReq) {
330 TheISA::IntReg overwrite_val;
331 bool overwrite_mem;
337 std::vector<uint8_t> overwrite_val(pkt->getSize());
332 uint64_t condition_val64;
333 uint32_t condition_val32;
334
335 if (!pmemAddr)
336 panic("Swap only works if there is real memory (i.e. null=False)");
338 uint64_t condition_val64;
339 uint32_t condition_val32;
340
341 if (!pmemAddr)
342 panic("Swap only works if there is real memory (i.e. null=False)");
337 assert(sizeof(TheISA::IntReg) >= pkt->getSize());
338
343
339 overwrite_mem = true;
344 bool overwrite_mem = true;
340 // keep a copy of our possible write value, and copy what is at the
341 // memory address into the packet
345 // keep a copy of our possible write value, and copy what is at the
346 // memory address into the packet
342 std::memcpy(&overwrite_val, pkt->getPtr(), pkt->getSize());
347 std::memcpy(&overwrite_val[0], pkt->getPtr<uint8_t>(), pkt->getSize());
343 std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
344
345 if (pkt->req->isCondSwap()) {
346 if (pkt->getSize() == sizeof(uint64_t)) {
347 condition_val64 = pkt->req->getExtraData();
348 overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
349 sizeof(uint64_t));
350 } else if (pkt->getSize() == sizeof(uint32_t)) {
351 condition_val32 = (uint32_t)pkt->req->getExtraData();
352 overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
353 sizeof(uint32_t));
354 } else
355 panic("Invalid size for conditional read/write\n");
356 }
357
358 if (overwrite_mem)
348 std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
349
350 if (pkt->req->isCondSwap()) {
351 if (pkt->getSize() == sizeof(uint64_t)) {
352 condition_val64 = pkt->req->getExtraData();
353 overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
354 sizeof(uint64_t));
355 } else if (pkt->getSize() == sizeof(uint32_t)) {
356 condition_val32 = (uint32_t)pkt->req->getExtraData();
357 overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
358 sizeof(uint32_t));
359 } else
360 panic("Invalid size for conditional read/write\n");
361 }
362
363 if (overwrite_mem)
359 std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
364 std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize());
360
361 assert(!pkt->req->isInstFetch());
362 TRACE_PACKET("Read/Write");
363 numOther[pkt->req->masterId()]++;
364 } else if (pkt->isRead()) {
365 assert(!pkt->isWrite());
366 if (pkt->isLLSC()) {
367 trackLoadLocked(pkt);

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366 assert(!pkt->req->isInstFetch());
367 TRACE_PACKET("Read/Write");
368 numOther[pkt->req->masterId()]++;
369 } else if (pkt->isRead()) {
370 assert(!pkt->isWrite());
371 if (pkt->isLLSC()) {
372 trackLoadLocked(pkt);

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