1/*
2 * Copyright (c) 2010-2012,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "mem/abstract_mem.hh"
46
47#include <vector>
48
49#include "arch/locked_mem.hh"
50#include "cpu/base.hh"
51#include "cpu/thread_context.hh"
52#include "debug/LLSC.hh"
53#include "debug/MemoryAccess.hh"
54#include "mem/packet_access.hh"
55#include "sim/system.hh"
56
57using namespace std;
58
59AbstractMemory::AbstractMemory(const Params *p) :
60 MemObject(p), range(params()->range), pmemAddr(NULL),
61 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
62 kvmMap(p->kvm_map), _system(NULL)
63{
64}
65
66void
67AbstractMemory::init()
68{
69 assert(system());
70
71 if (size() % _system->getPageBytes() != 0)
72 panic("Memory Size not divisible by page size\n");
73}
74
75void
76AbstractMemory::setBackingStore(uint8_t* pmem_addr)
77{
78 pmemAddr = pmem_addr;
79}
80
81void
82AbstractMemory::regStats()
83{
84 MemObject::regStats();
85
86 using namespace Stats;
87
88 assert(system());
89
90 bytesRead
91 .init(system()->maxMasters())
92 .name(name() + ".bytes_read")
93 .desc("Number of bytes read from this memory")
94 .flags(total | nozero | nonan)
95 ;
96 for (int i = 0; i < system()->maxMasters(); i++) {
97 bytesRead.subname(i, system()->getMasterName(i));
98 }
99 bytesInstRead
100 .init(system()->maxMasters())
101 .name(name() + ".bytes_inst_read")
102 .desc("Number of instructions bytes read from this memory")
103 .flags(total | nozero | nonan)
104 ;
105 for (int i = 0; i < system()->maxMasters(); i++) {
106 bytesInstRead.subname(i, system()->getMasterName(i));
107 }
108 bytesWritten
109 .init(system()->maxMasters())
110 .name(name() + ".bytes_written")
111 .desc("Number of bytes written to this memory")
112 .flags(total | nozero | nonan)
113 ;
114 for (int i = 0; i < system()->maxMasters(); i++) {
115 bytesWritten.subname(i, system()->getMasterName(i));
116 }
117 numReads
118 .init(system()->maxMasters())
119 .name(name() + ".num_reads")
120 .desc("Number of read requests responded to by this memory")
121 .flags(total | nozero | nonan)
122 ;
123 for (int i = 0; i < system()->maxMasters(); i++) {
124 numReads.subname(i, system()->getMasterName(i));
125 }
126 numWrites
127 .init(system()->maxMasters())
128 .name(name() + ".num_writes")
129 .desc("Number of write requests responded to by this memory")
130 .flags(total | nozero | nonan)
131 ;
132 for (int i = 0; i < system()->maxMasters(); i++) {
133 numWrites.subname(i, system()->getMasterName(i));
134 }
135 numOther
136 .init(system()->maxMasters())
137 .name(name() + ".num_other")
138 .desc("Number of other requests responded to by this memory")
139 .flags(total | nozero | nonan)
140 ;
141 for (int i = 0; i < system()->maxMasters(); i++) {
142 numOther.subname(i, system()->getMasterName(i));
143 }
144 bwRead
145 .name(name() + ".bw_read")
146 .desc("Total read bandwidth from this memory (bytes/s)")
147 .precision(0)
148 .prereq(bytesRead)
149 .flags(total | nozero | nonan)
150 ;
151 for (int i = 0; i < system()->maxMasters(); i++) {
152 bwRead.subname(i, system()->getMasterName(i));
153 }
154
155 bwInstRead
156 .name(name() + ".bw_inst_read")
157 .desc("Instruction read bandwidth from this memory (bytes/s)")
158 .precision(0)
159 .prereq(bytesInstRead)
160 .flags(total | nozero | nonan)
161 ;
162 for (int i = 0; i < system()->maxMasters(); i++) {
163 bwInstRead.subname(i, system()->getMasterName(i));
164 }
165 bwWrite
166 .name(name() + ".bw_write")
167 .desc("Write bandwidth from this memory (bytes/s)")
168 .precision(0)
169 .prereq(bytesWritten)
170 .flags(total | nozero | nonan)
171 ;
172 for (int i = 0; i < system()->maxMasters(); i++) {
173 bwWrite.subname(i, system()->getMasterName(i));
174 }
175 bwTotal
176 .name(name() + ".bw_total")
177 .desc("Total bandwidth to/from this memory (bytes/s)")
178 .precision(0)
179 .prereq(bwTotal)
180 .flags(total | nozero | nonan)
181 ;
182 for (int i = 0; i < system()->maxMasters(); i++) {
183 bwTotal.subname(i, system()->getMasterName(i));
184 }
185 bwRead = bytesRead / simSeconds;
186 bwInstRead = bytesInstRead / simSeconds;
187 bwWrite = bytesWritten / simSeconds;
188 bwTotal = (bytesRead + bytesWritten) / simSeconds;
189}
190
191AddrRange
192AbstractMemory::getAddrRange() const
193{
194 return range;
195}
196
197// Add load-locked to tracking list. Should only be called if the
198// operation is a load and the LLSC flag is set.
199void
200AbstractMemory::trackLoadLocked(PacketPtr pkt)
201{
202 const RequestPtr &req = pkt->req;
203 Addr paddr = LockedAddr::mask(req->getPaddr());
204
205 // first we check if we already have a locked addr for this
206 // xc. Since each xc only gets one, we just update the
207 // existing record with the new address.
208 list<LockedAddr>::iterator i;
209
210 for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
211 if (i->matchesContext(req)) {
212 DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
213 req->contextId(), paddr);
214 i->addr = paddr;
215 return;
216 }
217 }
218
219 // no record for this xc: need to allocate a new one
220 DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
221 req->contextId(), paddr);
222 lockedAddrList.push_front(LockedAddr(req));
223}
224
225
226// Called on *writes* only... both regular stores and
227// store-conditional operations. Check for conventional stores which
228// conflict with locked addresses, and for success/failure of store
229// conditionals.
230bool
231AbstractMemory::checkLockedAddrList(PacketPtr pkt)
232{
233 const RequestPtr &req = pkt->req;
234 Addr paddr = LockedAddr::mask(req->getPaddr());
235 bool isLLSC = pkt->isLLSC();
236
237 // Initialize return value. Non-conditional stores always
238 // succeed. Assume conditional stores will fail until proven
239 // otherwise.
240 bool allowStore = !isLLSC;
241
242 // Iterate over list. Note that there could be multiple matching records,
243 // as more than one context could have done a load locked to this location.
244 // Only remove records when we succeed in finding a record for (xc, addr);
245 // then, remove all records with this address. Failed store-conditionals do
246 // not blow unrelated reservations.
247 list<LockedAddr>::iterator i = lockedAddrList.begin();
248
249 if (isLLSC) {
250 while (i != lockedAddrList.end()) {
251 if (i->addr == paddr && i->matchesContext(req)) {
252 // it's a store conditional, and as far as the memory system can
253 // tell, the requesting context's lock is still valid.
254 DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
255 req->contextId(), paddr);
256 allowStore = true;
257 break;
258 }
259 // If we didn't find a match, keep searching! Someone else may well
260 // have a reservation on this line here but we may find ours in just
261 // a little while.
262 i++;
263 }
264 req->setExtraData(allowStore ? 1 : 0);
265 }
266 // LLSCs that succeeded AND non-LLSC stores both fall into here:
267 if (allowStore) {
268 // We write address paddr. However, there may be several entries with a
269 // reservation on this address (for other contextIds) and they must all
270 // be removed.
271 i = lockedAddrList.begin();
272 while (i != lockedAddrList.end()) {
273 if (i->addr == paddr) {
274 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
275 i->contextId, paddr);
276 ContextID owner_cid = i->contextId;
277 ContextID requester_cid = pkt->req->contextId();
278 if (owner_cid != requester_cid) {
279 ThreadContext* ctx = system()->getThreadContext(owner_cid);
280 TheISA::globalClearExclusive(ctx);
281 }
282 i = lockedAddrList.erase(i);
283 } else {
284 i++;
285 }
286 }
287 }
288
289 return allowStore;
290}
291
292static inline void
293tracePacket(System *sys, const char *label, PacketPtr pkt)
294{
295 int size = pkt->getSize();
296#if THE_ISA != NULL_ISA
297 if (size == 1 || size == 2 || size == 4 || size == 8) {
298 DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data "
299 "%#x %c\n", label, sys->getMasterName(pkt->req->masterId()),
300 size, pkt->getAddr(), pkt->getUintX(TheISA::GuestByteOrder),
301 pkt->req->isUncacheable() ? 'U' : 'C');
302 return;
303 }
304#endif
305 DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
306 label, sys->getMasterName(pkt->req->masterId()),
307 size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
308 DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
309}
310
311#if TRACING_ON
312# define TRACE_PACKET(A) tracePacket(system(), A, pkt)
313#else
314# define TRACE_PACKET(A)
315#endif
316
317void
318AbstractMemory::access(PacketPtr pkt)
319{
320 if (pkt->cacheResponding()) {
321 DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n",
322 pkt->getAddr());
323 return;
324 }
325
326 if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
327 DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n",
328 pkt->getAddr());
329 return;
330 }
331
332 assert(AddrRange(pkt->getAddr(),
333 pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range));
334
335 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
336
337 if (pkt->cmd == MemCmd::SwapReq) {
338 if (pkt->isAtomicOp()) {
339 if (pmemAddr) {
| 1/*
2 * Copyright (c) 2010-2012,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "mem/abstract_mem.hh"
46
47#include <vector>
48
49#include "arch/locked_mem.hh"
50#include "cpu/base.hh"
51#include "cpu/thread_context.hh"
52#include "debug/LLSC.hh"
53#include "debug/MemoryAccess.hh"
54#include "mem/packet_access.hh"
55#include "sim/system.hh"
56
57using namespace std;
58
59AbstractMemory::AbstractMemory(const Params *p) :
60 MemObject(p), range(params()->range), pmemAddr(NULL),
61 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
62 kvmMap(p->kvm_map), _system(NULL)
63{
64}
65
66void
67AbstractMemory::init()
68{
69 assert(system());
70
71 if (size() % _system->getPageBytes() != 0)
72 panic("Memory Size not divisible by page size\n");
73}
74
75void
76AbstractMemory::setBackingStore(uint8_t* pmem_addr)
77{
78 pmemAddr = pmem_addr;
79}
80
81void
82AbstractMemory::regStats()
83{
84 MemObject::regStats();
85
86 using namespace Stats;
87
88 assert(system());
89
90 bytesRead
91 .init(system()->maxMasters())
92 .name(name() + ".bytes_read")
93 .desc("Number of bytes read from this memory")
94 .flags(total | nozero | nonan)
95 ;
96 for (int i = 0; i < system()->maxMasters(); i++) {
97 bytesRead.subname(i, system()->getMasterName(i));
98 }
99 bytesInstRead
100 .init(system()->maxMasters())
101 .name(name() + ".bytes_inst_read")
102 .desc("Number of instructions bytes read from this memory")
103 .flags(total | nozero | nonan)
104 ;
105 for (int i = 0; i < system()->maxMasters(); i++) {
106 bytesInstRead.subname(i, system()->getMasterName(i));
107 }
108 bytesWritten
109 .init(system()->maxMasters())
110 .name(name() + ".bytes_written")
111 .desc("Number of bytes written to this memory")
112 .flags(total | nozero | nonan)
113 ;
114 for (int i = 0; i < system()->maxMasters(); i++) {
115 bytesWritten.subname(i, system()->getMasterName(i));
116 }
117 numReads
118 .init(system()->maxMasters())
119 .name(name() + ".num_reads")
120 .desc("Number of read requests responded to by this memory")
121 .flags(total | nozero | nonan)
122 ;
123 for (int i = 0; i < system()->maxMasters(); i++) {
124 numReads.subname(i, system()->getMasterName(i));
125 }
126 numWrites
127 .init(system()->maxMasters())
128 .name(name() + ".num_writes")
129 .desc("Number of write requests responded to by this memory")
130 .flags(total | nozero | nonan)
131 ;
132 for (int i = 0; i < system()->maxMasters(); i++) {
133 numWrites.subname(i, system()->getMasterName(i));
134 }
135 numOther
136 .init(system()->maxMasters())
137 .name(name() + ".num_other")
138 .desc("Number of other requests responded to by this memory")
139 .flags(total | nozero | nonan)
140 ;
141 for (int i = 0; i < system()->maxMasters(); i++) {
142 numOther.subname(i, system()->getMasterName(i));
143 }
144 bwRead
145 .name(name() + ".bw_read")
146 .desc("Total read bandwidth from this memory (bytes/s)")
147 .precision(0)
148 .prereq(bytesRead)
149 .flags(total | nozero | nonan)
150 ;
151 for (int i = 0; i < system()->maxMasters(); i++) {
152 bwRead.subname(i, system()->getMasterName(i));
153 }
154
155 bwInstRead
156 .name(name() + ".bw_inst_read")
157 .desc("Instruction read bandwidth from this memory (bytes/s)")
158 .precision(0)
159 .prereq(bytesInstRead)
160 .flags(total | nozero | nonan)
161 ;
162 for (int i = 0; i < system()->maxMasters(); i++) {
163 bwInstRead.subname(i, system()->getMasterName(i));
164 }
165 bwWrite
166 .name(name() + ".bw_write")
167 .desc("Write bandwidth from this memory (bytes/s)")
168 .precision(0)
169 .prereq(bytesWritten)
170 .flags(total | nozero | nonan)
171 ;
172 for (int i = 0; i < system()->maxMasters(); i++) {
173 bwWrite.subname(i, system()->getMasterName(i));
174 }
175 bwTotal
176 .name(name() + ".bw_total")
177 .desc("Total bandwidth to/from this memory (bytes/s)")
178 .precision(0)
179 .prereq(bwTotal)
180 .flags(total | nozero | nonan)
181 ;
182 for (int i = 0; i < system()->maxMasters(); i++) {
183 bwTotal.subname(i, system()->getMasterName(i));
184 }
185 bwRead = bytesRead / simSeconds;
186 bwInstRead = bytesInstRead / simSeconds;
187 bwWrite = bytesWritten / simSeconds;
188 bwTotal = (bytesRead + bytesWritten) / simSeconds;
189}
190
191AddrRange
192AbstractMemory::getAddrRange() const
193{
194 return range;
195}
196
197// Add load-locked to tracking list. Should only be called if the
198// operation is a load and the LLSC flag is set.
199void
200AbstractMemory::trackLoadLocked(PacketPtr pkt)
201{
202 const RequestPtr &req = pkt->req;
203 Addr paddr = LockedAddr::mask(req->getPaddr());
204
205 // first we check if we already have a locked addr for this
206 // xc. Since each xc only gets one, we just update the
207 // existing record with the new address.
208 list<LockedAddr>::iterator i;
209
210 for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
211 if (i->matchesContext(req)) {
212 DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
213 req->contextId(), paddr);
214 i->addr = paddr;
215 return;
216 }
217 }
218
219 // no record for this xc: need to allocate a new one
220 DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
221 req->contextId(), paddr);
222 lockedAddrList.push_front(LockedAddr(req));
223}
224
225
226// Called on *writes* only... both regular stores and
227// store-conditional operations. Check for conventional stores which
228// conflict with locked addresses, and for success/failure of store
229// conditionals.
230bool
231AbstractMemory::checkLockedAddrList(PacketPtr pkt)
232{
233 const RequestPtr &req = pkt->req;
234 Addr paddr = LockedAddr::mask(req->getPaddr());
235 bool isLLSC = pkt->isLLSC();
236
237 // Initialize return value. Non-conditional stores always
238 // succeed. Assume conditional stores will fail until proven
239 // otherwise.
240 bool allowStore = !isLLSC;
241
242 // Iterate over list. Note that there could be multiple matching records,
243 // as more than one context could have done a load locked to this location.
244 // Only remove records when we succeed in finding a record for (xc, addr);
245 // then, remove all records with this address. Failed store-conditionals do
246 // not blow unrelated reservations.
247 list<LockedAddr>::iterator i = lockedAddrList.begin();
248
249 if (isLLSC) {
250 while (i != lockedAddrList.end()) {
251 if (i->addr == paddr && i->matchesContext(req)) {
252 // it's a store conditional, and as far as the memory system can
253 // tell, the requesting context's lock is still valid.
254 DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
255 req->contextId(), paddr);
256 allowStore = true;
257 break;
258 }
259 // If we didn't find a match, keep searching! Someone else may well
260 // have a reservation on this line here but we may find ours in just
261 // a little while.
262 i++;
263 }
264 req->setExtraData(allowStore ? 1 : 0);
265 }
266 // LLSCs that succeeded AND non-LLSC stores both fall into here:
267 if (allowStore) {
268 // We write address paddr. However, there may be several entries with a
269 // reservation on this address (for other contextIds) and they must all
270 // be removed.
271 i = lockedAddrList.begin();
272 while (i != lockedAddrList.end()) {
273 if (i->addr == paddr) {
274 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
275 i->contextId, paddr);
276 ContextID owner_cid = i->contextId;
277 ContextID requester_cid = pkt->req->contextId();
278 if (owner_cid != requester_cid) {
279 ThreadContext* ctx = system()->getThreadContext(owner_cid);
280 TheISA::globalClearExclusive(ctx);
281 }
282 i = lockedAddrList.erase(i);
283 } else {
284 i++;
285 }
286 }
287 }
288
289 return allowStore;
290}
291
292static inline void
293tracePacket(System *sys, const char *label, PacketPtr pkt)
294{
295 int size = pkt->getSize();
296#if THE_ISA != NULL_ISA
297 if (size == 1 || size == 2 || size == 4 || size == 8) {
298 DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data "
299 "%#x %c\n", label, sys->getMasterName(pkt->req->masterId()),
300 size, pkt->getAddr(), pkt->getUintX(TheISA::GuestByteOrder),
301 pkt->req->isUncacheable() ? 'U' : 'C');
302 return;
303 }
304#endif
305 DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
306 label, sys->getMasterName(pkt->req->masterId()),
307 size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
308 DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
309}
310
311#if TRACING_ON
312# define TRACE_PACKET(A) tracePacket(system(), A, pkt)
313#else
314# define TRACE_PACKET(A)
315#endif
316
317void
318AbstractMemory::access(PacketPtr pkt)
319{
320 if (pkt->cacheResponding()) {
321 DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n",
322 pkt->getAddr());
323 return;
324 }
325
326 if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
327 DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n",
328 pkt->getAddr());
329 return;
330 }
331
332 assert(AddrRange(pkt->getAddr(),
333 pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range));
334
335 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
336
337 if (pkt->cmd == MemCmd::SwapReq) {
338 if (pkt->isAtomicOp()) {
339 if (pmemAddr) {
|