1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "debug/LLSC.hh"
48#include "debug/MemoryAccess.hh"
49#include "mem/abstract_mem.hh"
50#include "mem/packet_access.hh"
51#include "sim/system.hh"
52
53using namespace std;
54
55AbstractMemory::AbstractMemory(const Params *p) :
56 MemObject(p), range(params()->range), pmemAddr(NULL),
57 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
58 _system(NULL)
59{
60 if (size() % TheISA::PageBytes != 0)
61 panic("Memory Size not divisible by page size\n");
62}
63
64void
65AbstractMemory::setBackingStore(uint8_t* pmem_addr)
66{
67 pmemAddr = pmem_addr;
68}
69
70void
71AbstractMemory::regStats()
72{
73 using namespace Stats;
74
75 assert(system());
76
77 bytesRead
78 .init(system()->maxMasters())
79 .name(name() + ".bytes_read")
80 .desc("Number of bytes read from this memory")
81 .flags(total | nozero | nonan)
82 ;
83 for (int i = 0; i < system()->maxMasters(); i++) {
84 bytesRead.subname(i, system()->getMasterName(i));
85 }
86 bytesInstRead
87 .init(system()->maxMasters())
88 .name(name() + ".bytes_inst_read")
89 .desc("Number of instructions bytes read from this memory")
90 .flags(total | nozero | nonan)
91 ;
92 for (int i = 0; i < system()->maxMasters(); i++) {
93 bytesInstRead.subname(i, system()->getMasterName(i));
94 }
95 bytesWritten
96 .init(system()->maxMasters())
97 .name(name() + ".bytes_written")
98 .desc("Number of bytes written to this memory")
99 .flags(total | nozero | nonan)
100 ;
101 for (int i = 0; i < system()->maxMasters(); i++) {
102 bytesWritten.subname(i, system()->getMasterName(i));
103 }
104 numReads
105 .init(system()->maxMasters())
106 .name(name() + ".num_reads")
107 .desc("Number of read requests responded to by this memory")
108 .flags(total | nozero | nonan)
109 ;
110 for (int i = 0; i < system()->maxMasters(); i++) {
111 numReads.subname(i, system()->getMasterName(i));
112 }
113 numWrites
114 .init(system()->maxMasters())
115 .name(name() + ".num_writes")
116 .desc("Number of write requests responded to by this memory")
117 .flags(total | nozero | nonan)
118 ;
119 for (int i = 0; i < system()->maxMasters(); i++) {
120 numWrites.subname(i, system()->getMasterName(i));
121 }
122 numOther
123 .init(system()->maxMasters())
124 .name(name() + ".num_other")
125 .desc("Number of other requests responded to by this memory")
126 .flags(total | nozero | nonan)
127 ;
128 for (int i = 0; i < system()->maxMasters(); i++) {
129 numOther.subname(i, system()->getMasterName(i));
130 }
131 bwRead
132 .name(name() + ".bw_read")
133 .desc("Total read bandwidth from this memory (bytes/s)")
134 .precision(0)
135 .prereq(bytesRead)
136 .flags(total | nozero | nonan)
137 ;
138 for (int i = 0; i < system()->maxMasters(); i++) {
139 bwRead.subname(i, system()->getMasterName(i));
140 }
141
142 bwInstRead
143 .name(name() + ".bw_inst_read")
144 .desc("Instruction read bandwidth from this memory (bytes/s)")
145 .precision(0)
146 .prereq(bytesInstRead)
147 .flags(total | nozero | nonan)
148 ;
149 for (int i = 0; i < system()->maxMasters(); i++) {
150 bwInstRead.subname(i, system()->getMasterName(i));
151 }
152 bwWrite
153 .name(name() + ".bw_write")
154 .desc("Write bandwidth from this memory (bytes/s)")
155 .precision(0)
156 .prereq(bytesWritten)
157 .flags(total | nozero | nonan)
158 ;
159 for (int i = 0; i < system()->maxMasters(); i++) {
160 bwWrite.subname(i, system()->getMasterName(i));
161 }
162 bwTotal
163 .name(name() + ".bw_total")
164 .desc("Total bandwidth to/from this memory (bytes/s)")
165 .precision(0)
166 .prereq(bwTotal)
167 .flags(total | nozero | nonan)
168 ;
169 for (int i = 0; i < system()->maxMasters(); i++) {
170 bwTotal.subname(i, system()->getMasterName(i));
171 }
172 bwRead = bytesRead / simSeconds;
173 bwInstRead = bytesInstRead / simSeconds;
174 bwWrite = bytesWritten / simSeconds;
175 bwTotal = (bytesRead + bytesWritten) / simSeconds;
176}
177
178AddrRange
179AbstractMemory::getAddrRange() const
180{
181 return range;
182}
183
184// Add load-locked to tracking list. Should only be called if the
185// operation is a load and the LLSC flag is set.
186void
187AbstractMemory::trackLoadLocked(PacketPtr pkt)
188{
189 Request *req = pkt->req;
190 Addr paddr = LockedAddr::mask(req->getPaddr());
191
192 // first we check if we already have a locked addr for this
193 // xc. Since each xc only gets one, we just update the
194 // existing record with the new address.
195 list<LockedAddr>::iterator i;
196
197 for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
198 if (i->matchesContext(req)) {
199 DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
200 req->contextId(), paddr);
201 i->addr = paddr;
202 return;
203 }
204 }
205
206 // no record for this xc: need to allocate a new one
207 DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
208 req->contextId(), paddr);
209 lockedAddrList.push_front(LockedAddr(req));
210}
211
212
213// Called on *writes* only... both regular stores and
214// store-conditional operations. Check for conventional stores which
215// conflict with locked addresses, and for success/failure of store
216// conditionals.
217bool
218AbstractMemory::checkLockedAddrList(PacketPtr pkt)
219{
220 Request *req = pkt->req;
221 Addr paddr = LockedAddr::mask(req->getPaddr());
222 bool isLLSC = pkt->isLLSC();
223
224 // Initialize return value. Non-conditional stores always
225 // succeed. Assume conditional stores will fail until proven
226 // otherwise.
227 bool allowStore = !isLLSC;
228
229 // Iterate over list. Note that there could be multiple matching records,
230 // as more than one context could have done a load locked to this location.
231 // Only remove records when we succeed in finding a record for (xc, addr);
232 // then, remove all records with this address. Failed store-conditionals do
233 // not blow unrelated reservations.
234 list<LockedAddr>::iterator i = lockedAddrList.begin();
235
236 if (isLLSC) {
237 while (i != lockedAddrList.end()) {
238 if (i->addr == paddr && i->matchesContext(req)) {
239 // it's a store conditional, and as far as the memory system can
240 // tell, the requesting context's lock is still valid.
241 DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
242 req->contextId(), paddr);
243 allowStore = true;
244 break;
245 }
246 // If we didn't find a match, keep searching! Someone else may well
247 // have a reservation on this line here but we may find ours in just
248 // a little while.
249 i++;
250 }
251 req->setExtraData(allowStore ? 1 : 0);
252 }
253 // LLSCs that succeeded AND non-LLSC stores both fall into here:
254 if (allowStore) {
255 // We write address paddr. However, there may be several entries with a
256 // reservation on this address (for other contextIds) and they must all
257 // be removed.
258 i = lockedAddrList.begin();
259 while (i != lockedAddrList.end()) {
260 if (i->addr == paddr) {
261 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
262 i->contextId, paddr);
263 i = lockedAddrList.erase(i);
264 } else {
265 i++;
266 }
267 }
268 }
269
270 return allowStore;
271}
272
273
274#if TRACING_ON
275
276#define CASE(A, T) \
277 case sizeof(T): \
278 DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \
279 "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\
280 pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \
281 pkt->req->isUncacheable() ? 'U' : 'C'); \
282 break
283
284
285#define TRACE_PACKET(A) \
286 do { \
287 switch (pkt->getSize()) { \
288 CASE(A, uint64_t); \
289 CASE(A, uint32_t); \
290 CASE(A, uint16_t); \
291 CASE(A, uint8_t); \
292 default: \
293 DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\
294 A, system()->getMasterName(pkt->req->masterId()), \
295 pkt->getSize(), pkt->getAddr(), \
296 pkt->req->isUncacheable() ? 'U' : 'C'); \
297 DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize()); \
298 } \
299 } while (0)
300
301#else
302
303#define TRACE_PACKET(A)
304
305#endif
306
307void
308AbstractMemory::access(PacketPtr pkt)
309{
310 assert(AddrRange(pkt->getAddr(),
311 pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
312
313 if (pkt->memInhibitAsserted()) {
314 DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
315 pkt->getAddr());
316 return;
317 }
318
319 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
320
321 if (pkt->cmd == MemCmd::SwapReq) {
322 TheISA::IntReg overwrite_val;
323 bool overwrite_mem;
324 uint64_t condition_val64;
325 uint32_t condition_val32;
326
327 if (!pmemAddr)
328 panic("Swap only works if there is real memory (i.e. null=False)");
329 assert(sizeof(TheISA::IntReg) >= pkt->getSize());
330
331 overwrite_mem = true;
332 // keep a copy of our possible write value, and copy what is at the
333 // memory address into the packet
334 std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize());
335 std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
336
337 if (pkt->req->isCondSwap()) {
338 if (pkt->getSize() == sizeof(uint64_t)) {
339 condition_val64 = pkt->req->getExtraData();
340 overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
341 sizeof(uint64_t));
342 } else if (pkt->getSize() == sizeof(uint32_t)) {
343 condition_val32 = (uint32_t)pkt->req->getExtraData();
344 overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
345 sizeof(uint32_t));
346 } else
347 panic("Invalid size for conditional read/write\n");
348 }
349
350 if (overwrite_mem)
351 std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
352
353 assert(!pkt->req->isInstFetch());
354 TRACE_PACKET("Read/Write");
355 numOther[pkt->req->masterId()]++;
356 } else if (pkt->isRead()) {
357 assert(!pkt->isWrite());
358 if (pkt->isLLSC()) {
359 trackLoadLocked(pkt);
360 }
361 if (pmemAddr)
362 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
363 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
364 numReads[pkt->req->masterId()]++;
365 bytesRead[pkt->req->masterId()] += pkt->getSize();
366 if (pkt->req->isInstFetch())
367 bytesInstRead[pkt->req->masterId()] += pkt->getSize();
368 } else if (pkt->isWrite()) {
369 if (writeOK(pkt)) {
370 if (pmemAddr) {
371 memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
372 DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
373 __func__, pkt->getSize(), pkt->getAddr());
374 }
375 assert(!pkt->req->isInstFetch());
376 TRACE_PACKET("Write");
377 numWrites[pkt->req->masterId()]++;
378 bytesWritten[pkt->req->masterId()] += pkt->getSize();
379 }
380 } else if (pkt->isInvalidate()) {
381 // no need to do anything
382 } else {
383 panic("unimplemented");
384 }
385
386 if (pkt->needsResponse()) {
387 pkt->makeResponse();
388 }
389}
390
391void
392AbstractMemory::functionalAccess(PacketPtr pkt)
393{
394 assert(AddrRange(pkt->getAddr(),
395 pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
396
397 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
398
399 if (pkt->isRead()) {
400 if (pmemAddr)
401 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
402 TRACE_PACKET("Read");
403 pkt->makeResponse();
404 } else if (pkt->isWrite()) {
405 if (pmemAddr)
406 memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
407 TRACE_PACKET("Write");
408 pkt->makeResponse();
409 } else if (pkt->isPrint()) {
410 Packet::PrintReqState *prs =
411 dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
412 assert(prs);
413 // Need to call printLabels() explicitly since we're not going
414 // through printObj().
415 prs->printLabels();
416 // Right now we just print the single byte at the specified address.
417 ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
418 } else {
419 panic("AbstractMemory: unimplemented functional command %s",
420 pkt->cmdString());
421 }
422}