1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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336 }
337
338 assert(AddrRange(pkt->getAddr(),
339 pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range));
340
341 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
342
343 if (pkt->cmd == MemCmd::SwapReq) {
344 std::vector<uint8_t> overwrite_val(pkt->getSize());
345 uint64_t condition_val64;
346 uint32_t condition_val32;
347
348 if (!pmemAddr)
349 panic("Swap only works if there is real memory (i.e. null=False)");
350
351 bool overwrite_mem = true;
352 // keep a copy of our possible write value, and copy what is at the
353 // memory address into the packet
354 std::memcpy(&overwrite_val[0], pkt->getConstPtr(),
355 pkt->getSize());
356 std::memcpy(pkt->getPtr(), hostAddr, pkt->getSize());
357
358 if (pkt->req->isCondSwap()) {
359 if (pkt->getSize() == sizeof(uint64_t)) {
360 condition_val64 = pkt->req->getExtraData();
361 overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
362 sizeof(uint64_t));
363 } else if (pkt->getSize() == sizeof(uint32_t)) {
364 condition_val32 = (uint32_t)pkt->req->getExtraData();
365 overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
366 sizeof(uint32_t));
367 } else
368 panic("Invalid size for conditional read/write\n");
369 }
370
371 if (overwrite_mem)
372 std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize());
373
374 assert(!pkt->req->isInstFetch());
375 TRACE_PACKET("Read/Write");
376 numOther[pkt->req->masterId()]++;
377 } else if (pkt->isRead()) {
378 assert(!pkt->isWrite());
379 if (pkt->isLLSC()) {
380 trackLoadLocked(pkt);
381 }
382 if (pmemAddr)
383 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
384 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");

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