1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/LLSC.hh"
50#include "debug/MemoryAccess.hh"
51#include "mem/abstract_mem.hh"
52#include "mem/packet_access.hh"
53#include "sim/system.hh"
54
55using namespace std;
56
57AbstractMemory::AbstractMemory(const Params *p) :
58 MemObject(p), range(params()->range), pmemAddr(NULL),
59 confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
60 _system(NULL)
61{
62 if (size() % TheISA::PageBytes != 0)
63 panic("Memory Size not divisible by page size\n");
64}
65
66void
67AbstractMemory::setBackingStore(uint8_t* pmem_addr)
68{
69 pmemAddr = pmem_addr;
70}
71
72void
73AbstractMemory::regStats()
74{
75 using namespace Stats;
76
77 assert(system());
78
79 bytesRead
80 .init(system()->maxMasters())
81 .name(name() + ".bytes_read")
82 .desc("Number of bytes read from this memory")
83 .flags(total | nozero | nonan)
84 ;
85 for (int i = 0; i < system()->maxMasters(); i++) {
86 bytesRead.subname(i, system()->getMasterName(i));
87 }
88 bytesInstRead
89 .init(system()->maxMasters())
90 .name(name() + ".bytes_inst_read")
91 .desc("Number of instructions bytes read from this memory")
92 .flags(total | nozero | nonan)
93 ;
94 for (int i = 0; i < system()->maxMasters(); i++) {
95 bytesInstRead.subname(i, system()->getMasterName(i));
96 }
97 bytesWritten
98 .init(system()->maxMasters())
99 .name(name() + ".bytes_written")
100 .desc("Number of bytes written to this memory")
101 .flags(total | nozero | nonan)
102 ;
103 for (int i = 0; i < system()->maxMasters(); i++) {
104 bytesWritten.subname(i, system()->getMasterName(i));
105 }
106 numReads
107 .init(system()->maxMasters())
108 .name(name() + ".num_reads")
109 .desc("Number of read requests responded to by this memory")
110 .flags(total | nozero | nonan)
111 ;
112 for (int i = 0; i < system()->maxMasters(); i++) {
113 numReads.subname(i, system()->getMasterName(i));
114 }
115 numWrites
116 .init(system()->maxMasters())
117 .name(name() + ".num_writes")
118 .desc("Number of write requests responded to by this memory")
119 .flags(total | nozero | nonan)
120 ;
121 for (int i = 0; i < system()->maxMasters(); i++) {
122 numWrites.subname(i, system()->getMasterName(i));
123 }
124 numOther
125 .init(system()->maxMasters())
126 .name(name() + ".num_other")
127 .desc("Number of other requests responded to by this memory")
128 .flags(total | nozero | nonan)
129 ;
130 for (int i = 0; i < system()->maxMasters(); i++) {
131 numOther.subname(i, system()->getMasterName(i));
132 }
133 bwRead
134 .name(name() + ".bw_read")
135 .desc("Total read bandwidth from this memory (bytes/s)")
136 .precision(0)
137 .prereq(bytesRead)
138 .flags(total | nozero | nonan)
139 ;
140 for (int i = 0; i < system()->maxMasters(); i++) {
141 bwRead.subname(i, system()->getMasterName(i));
142 }
143
144 bwInstRead
145 .name(name() + ".bw_inst_read")
146 .desc("Instruction read bandwidth from this memory (bytes/s)")
147 .precision(0)
148 .prereq(bytesInstRead)
149 .flags(total | nozero | nonan)
150 ;
151 for (int i = 0; i < system()->maxMasters(); i++) {
152 bwInstRead.subname(i, system()->getMasterName(i));
153 }
154 bwWrite
155 .name(name() + ".bw_write")
156 .desc("Write bandwidth from this memory (bytes/s)")
157 .precision(0)
158 .prereq(bytesWritten)
159 .flags(total | nozero | nonan)
160 ;
161 for (int i = 0; i < system()->maxMasters(); i++) {
162 bwWrite.subname(i, system()->getMasterName(i));
163 }
164 bwTotal
165 .name(name() + ".bw_total")
166 .desc("Total bandwidth to/from this memory (bytes/s)")
167 .precision(0)
168 .prereq(bwTotal)
169 .flags(total | nozero | nonan)
170 ;
171 for (int i = 0; i < system()->maxMasters(); i++) {
172 bwTotal.subname(i, system()->getMasterName(i));
173 }
174 bwRead = bytesRead / simSeconds;
175 bwInstRead = bytesInstRead / simSeconds;
176 bwWrite = bytesWritten / simSeconds;
177 bwTotal = (bytesRead + bytesWritten) / simSeconds;
178}
179
180AddrRange
181AbstractMemory::getAddrRange() const
182{
183 return range;
184}
185
186// Add load-locked to tracking list. Should only be called if the
187// operation is a load and the LLSC flag is set.
188void
189AbstractMemory::trackLoadLocked(PacketPtr pkt)
190{
191 Request *req = pkt->req;
192 Addr paddr = LockedAddr::mask(req->getPaddr());
193
194 // first we check if we already have a locked addr for this
195 // xc. Since each xc only gets one, we just update the
196 // existing record with the new address.
197 list<LockedAddr>::iterator i;
198
199 for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
200 if (i->matchesContext(req)) {
201 DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
202 req->contextId(), paddr);
203 i->addr = paddr;
204 return;
205 }
206 }
207
208 // no record for this xc: need to allocate a new one
209 DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
210 req->contextId(), paddr);
211 lockedAddrList.push_front(LockedAddr(req));
212}
213
214
215// Called on *writes* only... both regular stores and
216// store-conditional operations. Check for conventional stores which
217// conflict with locked addresses, and for success/failure of store
218// conditionals.
219bool
220AbstractMemory::checkLockedAddrList(PacketPtr pkt)
221{
222 Request *req = pkt->req;
223 Addr paddr = LockedAddr::mask(req->getPaddr());
224 bool isLLSC = pkt->isLLSC();
225
226 // Initialize return value. Non-conditional stores always
227 // succeed. Assume conditional stores will fail until proven
228 // otherwise.
229 bool allowStore = !isLLSC;
230
231 // Iterate over list. Note that there could be multiple matching records,
232 // as more than one context could have done a load locked to this location.
233 // Only remove records when we succeed in finding a record for (xc, addr);
234 // then, remove all records with this address. Failed store-conditionals do
235 // not blow unrelated reservations.
236 list<LockedAddr>::iterator i = lockedAddrList.begin();
237
238 if (isLLSC) {
239 while (i != lockedAddrList.end()) {
240 if (i->addr == paddr && i->matchesContext(req)) {
241 // it's a store conditional, and as far as the memory system can
242 // tell, the requesting context's lock is still valid.
243 DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
244 req->contextId(), paddr);
245 allowStore = true;
246 break;
247 }
248 // If we didn't find a match, keep searching! Someone else may well
249 // have a reservation on this line here but we may find ours in just
250 // a little while.
251 i++;
252 }
253 req->setExtraData(allowStore ? 1 : 0);
254 }
255 // LLSCs that succeeded AND non-LLSC stores both fall into here:
256 if (allowStore) {
257 // We write address paddr. However, there may be several entries with a
258 // reservation on this address (for other contextIds) and they must all
259 // be removed.
260 i = lockedAddrList.begin();
261 while (i != lockedAddrList.end()) {
262 if (i->addr == paddr) {
263 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
264 i->contextId, paddr);
265 // For ARM, a spinlock would typically include a Wait
266 // For Event (WFE) to conserve energy. The ARMv8
267 // architecture specifies that an event is
268 // automatically generated when clearing the exclusive
269 // monitor to wake up the processor in WFE.
270 system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup();
271 i = lockedAddrList.erase(i);
272 } else {
273 i++;
274 }
275 }
276 }
277
278 return allowStore;
279}
280
281
282#if TRACING_ON
283
284#define CASE(A, T) \
285 case sizeof(T): \
286 DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \
287 "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\
288 pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \
289 pkt->req->isUncacheable() ? 'U' : 'C'); \
290 break
291
292
293#define TRACE_PACKET(A) \
294 do { \
295 switch (pkt->getSize()) { \
296 CASE(A, uint64_t); \
297 CASE(A, uint32_t); \
298 CASE(A, uint16_t); \
299 CASE(A, uint8_t); \
300 default: \
301 DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\
302 A, system()->getMasterName(pkt->req->masterId()), \
303 pkt->getSize(), pkt->getAddr(), \
304 pkt->req->isUncacheable() ? 'U' : 'C'); \
305 DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize()); \
306 } \
307 } while (0)
308
309#else
310
311#define TRACE_PACKET(A)
312
313#endif
314
315void
316AbstractMemory::access(PacketPtr pkt)
317{
318 assert(AddrRange(pkt->getAddr(),
319 pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
320
321 if (pkt->memInhibitAsserted()) {
322 DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
323 pkt->getAddr());
324 return;
325 }
326
327 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
328
329 if (pkt->cmd == MemCmd::SwapReq) {
330 TheISA::IntReg overwrite_val;
331 bool overwrite_mem;
332 uint64_t condition_val64;
333 uint32_t condition_val32;
334
335 if (!pmemAddr)
336 panic("Swap only works if there is real memory (i.e. null=False)");
337 assert(sizeof(TheISA::IntReg) >= pkt->getSize());
338
339 overwrite_mem = true;
340 // keep a copy of our possible write value, and copy what is at the
341 // memory address into the packet
342 std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize());
343 std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
344
345 if (pkt->req->isCondSwap()) {
346 if (pkt->getSize() == sizeof(uint64_t)) {
347 condition_val64 = pkt->req->getExtraData();
348 overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
349 sizeof(uint64_t));
350 } else if (pkt->getSize() == sizeof(uint32_t)) {
351 condition_val32 = (uint32_t)pkt->req->getExtraData();
352 overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
353 sizeof(uint32_t));
354 } else
355 panic("Invalid size for conditional read/write\n");
356 }
357
358 if (overwrite_mem)
359 std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
360
361 assert(!pkt->req->isInstFetch());
362 TRACE_PACKET("Read/Write");
363 numOther[pkt->req->masterId()]++;
364 } else if (pkt->isRead()) {
365 assert(!pkt->isWrite());
366 if (pkt->isLLSC()) {
367 trackLoadLocked(pkt);
368 }
369 if (pmemAddr)
370 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
371 TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
372 numReads[pkt->req->masterId()]++;
373 bytesRead[pkt->req->masterId()] += pkt->getSize();
374 if (pkt->req->isInstFetch())
375 bytesInstRead[pkt->req->masterId()] += pkt->getSize();
376 } else if (pkt->isWrite()) {
377 if (writeOK(pkt)) {
378 if (pmemAddr) {
379 memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
380 DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
381 __func__, pkt->getSize(), pkt->getAddr());
382 }
383 assert(!pkt->req->isInstFetch());
384 TRACE_PACKET("Write");
385 numWrites[pkt->req->masterId()]++;
386 bytesWritten[pkt->req->masterId()] += pkt->getSize();
387 }
388 } else if (pkt->isInvalidate()) {
389 // no need to do anything
390 } else {
391 panic("unimplemented");
392 }
393
394 if (pkt->needsResponse()) {
395 pkt->makeResponse();
396 }
397}
398
399void
400AbstractMemory::functionalAccess(PacketPtr pkt)
401{
402 assert(AddrRange(pkt->getAddr(),
403 pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
404
405 uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
406
407 if (pkt->isRead()) {
408 if (pmemAddr)
409 memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
410 TRACE_PACKET("Read");
411 pkt->makeResponse();
412 } else if (pkt->isWrite()) {
413 if (pmemAddr)
414 memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
415 TRACE_PACKET("Write");
416 pkt->makeResponse();
417 } else if (pkt->isPrint()) {
418 Packet::PrintReqState *prs =
419 dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
420 assert(prs);
421 // Need to call printLabels() explicitly since we're not going
422 // through printObj().
423 prs->printLabels();
424 // Right now we just print the single byte at the specified address.
425 ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
426 } else {
427 panic("AbstractMemory: unimplemented functional command %s",
428 pkt->cmdString());
429 }
430}