XBar.py (13665:9c7fe3811b88) XBar.py (13892:0182a0601f66)
1# Copyright (c) 2012, 2015, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.objects.System import System
43from m5.params import *
44from m5.proxy import *
45from m5.SimObject import SimObject
46
1# Copyright (c) 2012, 2015, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 30 unchanged lines hidden (view full) ---

39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.objects.System import System
43from m5.params import *
44from m5.proxy import *
45from m5.SimObject import SimObject
46
47from m5.objects.MemObject import MemObject
47from m5.objects.ClockedObject import ClockedObject
48
48
49class BaseXBar(MemObject):
49class BaseXBar(ClockedObject):
50 type = 'BaseXBar'
51 abstract = True
52 cxx_header = "mem/xbar.hh"
53
54 slave = VectorSlavePort("Vector port for connecting masters")
55 master = VectorMasterPort("Vector port for connecting slaves")
56
57 # Latencies governing the time taken for the variuos paths a

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50 type = 'BaseXBar'
51 abstract = True
52 cxx_header = "mem/xbar.hh"
53
54 slave = VectorSlavePort("Vector port for connecting masters")
55 master = VectorMasterPort("Vector port for connecting slaves")
56
57 # Latencies governing the time taken for the variuos paths a

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