XBar.py (10720:67b3e74de9ae) XBar.py (11132:fbd597034299)
1# Copyright (c) 2012, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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107 cxx_header = "mem/snoop_filter.hh"
108
109 # Lookup latency of the snoop filter, added to requests that pass
110 # through a coherent crossbar.
111 lookup_latency = Param.Cycles(1, "Lookup latency")
112
113 system = Param.System(Parent.any, "System that the crossbar belongs to.")
114
1# Copyright (c) 2012, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 98 unchanged lines hidden (view full) ---

107 cxx_header = "mem/snoop_filter.hh"
108
109 # Lookup latency of the snoop filter, added to requests that pass
110 # through a coherent crossbar.
111 lookup_latency = Param.Cycles(1, "Lookup latency")
112
113 system = Param.System(Parent.any, "System that the crossbar belongs to.")
114
115 # Sanity check on max capacity to track, adjust if needed.
116 max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
117
115# We use a coherent crossbar to connect multiple masters to the L2
116# caches. Normally this crossbar would be part of the cache itself.
117class L2XBar(CoherentXBar):
118 # 256-bit crossbar by default
119 width = 32
120
121 # Assume that most of this is covered by the cache latencies, with
122 # no more than a single pipeline stage for any packet.
123 frontend_latency = 1
124 forward_latency = 0
125 response_latency = 1
126 snoop_response_latency = 1
127
118# We use a coherent crossbar to connect multiple masters to the L2
119# caches. Normally this crossbar would be part of the cache itself.
120class L2XBar(CoherentXBar):
121 # 256-bit crossbar by default
122 width = 32
123
124 # Assume that most of this is covered by the cache latencies, with
125 # no more than a single pipeline stage for any packet.
126 frontend_latency = 1
127 forward_latency = 0
128 response_latency = 1
129 snoop_response_latency = 1
130
131 # Use a snoop-filter by default, and set the latency to zero as
132 # the lookup is assumed to overlap with the frontend latency of
133 # the crossbar
134 snoop_filter = SnoopFilter(lookup_latency = 0)
135
128# One of the key coherent crossbar instances is the system
129# interconnect, tying together the CPU clusters, GPUs, and any I/O
130# coherent masters, and DRAM controllers.
131class SystemXBar(CoherentXBar):
132 # 128-bit crossbar by default
133 width = 16
134
135 # A handful pipeline stages for each portion of the latency

--- 19 unchanged lines hidden --- 		136# One of the key coherent crossbar instances is the system
137# interconnect, tying together the CPU clusters, GPUs, and any I/O
138# coherent masters, and DRAM controllers.
139class SystemXBar(CoherentXBar):
140 # 128-bit crossbar by default
141 width = 16
142
143 # A handful pipeline stages for each portion of the latency

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