1# Copyright (c) 2012, 2015 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 34 unchanged lines hidden (view full) --- 44from m5.params import * 45from m5.proxy import * 46from m5.SimObject import SimObject 47 48class BaseXBar(MemObject): 49 type = 'BaseXBar' 50 abstract = True 51 cxx_header = "mem/xbar.hh" |
52 |
53 slave = VectorSlavePort("Vector port for connecting masters") 54 master = VectorMasterPort("Vector port for connecting slaves") 55 56 # Latencies governing the time taken for the variuos paths a 57 # packet has through the crossbar. Note that the crossbar itself 58 # does not add the latency due to assumptions in the coherency 59 # mechanism. Instead the latency is annotated on the packet and 60 # left to the neighbouring modules. 61 # 62 # A request incurs the frontend latency, possibly snoop filter 63 # lookup latency, and forward latency. A response incurs the 64 # response latency. Frontend latency encompasses arbitration and 65 # deciding what to do when a request arrives. the forward latency 66 # is the latency involved once a decision is made to forward the 67 # request. The response latency, is similar to the forward 68 # latency, but for responses rather than requests. 69 frontend_latency = Param.Cycles(3, "Frontend latency") 70 forward_latency = Param.Cycles(4, "Forward latency") 71 response_latency = Param.Cycles(2, "Response latency") 72 73 # Width governing the throughput of the crossbar 74 width = Param.Unsigned(8, "Datapath width per port (bytes)") 75 |
76 # The default port can be left unconnected, or be used to connect 77 # a default slave port 78 default = MasterPort("Port for connecting an optional default slave") 79 80 # The default port can be used unconditionally, or based on 81 # address range, in which case it may overlap with other 82 # ports. The default range is always checked first, thus creating 83 # a two-level hierarchical lookup. This is useful e.g. for the PCI --- 4 unchanged lines hidden (view full) --- 88class NoncoherentXBar(BaseXBar): 89 type = 'NoncoherentXBar' 90 cxx_header = "mem/noncoherent_xbar.hh" 91 92class CoherentXBar(BaseXBar): 93 type = 'CoherentXBar' 94 cxx_header = "mem/coherent_xbar.hh" 95 |
96 # The coherent crossbar additionally has snoop responses that are 97 # forwarded after a specific latency. 98 snoop_response_latency = Param.Cycles(4, "Snoop response latency") 99 100 # An optional snoop filter 101 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter") 102 |
103 system = Param.System(Parent.any, "System that the crossbar belongs to.") |
104 105class SnoopFilter(SimObject): 106 type = 'SnoopFilter' 107 cxx_header = "mem/snoop_filter.hh" |
108 |
109 # Lookup latency of the snoop filter, added to requests that pass 110 # through a coherent crossbar. 111 lookup_latency = Param.Cycles(1, "Lookup latency") 112 |
113 system = Param.System(Parent.any, "System that the crossbar belongs to.") |