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< frontend_latency = Param.Cycles(3, "Frontend latency")
< forward_latency = Param.Cycles(4, "Forward latency")
< response_latency = Param.Cycles(2, "Response latency")
---
> frontend_latency = Param.Cycles("Frontend latency")
> forward_latency = Param.Cycles("Forward latency")
> response_latency = Param.Cycles("Response latency")
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< width = Param.Unsigned(8, "Datapath width per port (bytes)")
---
> width = Param.Unsigned("Datapath width per port (bytes)")
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< snoop_response_latency = Param.Cycles(4, "Snoop response latency")
---
> snoop_response_latency = Param.Cycles("Snoop response latency")
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>
> # We use a coherent crossbar to connect multiple masters to the L2
> # caches. Normally this crossbar would be part of the cache itself.
> class L2XBar(CoherentXBar):
> # 256-bit crossbar by default
> width = 32
>
> # Assume that most of this is covered by the cache latencies, with
> # no more than a single pipeline stage for any packet.
> frontend_latency = 1
> forward_latency = 0
> response_latency = 1
> snoop_response_latency = 1
>
> # One of the key coherent crossbar instances is the system
> # interconnect, tying together the CPU clusters, GPUs, and any I/O
> # coherent masters, and DRAM controllers.
> class SystemXBar(CoherentXBar):
> # 128-bit crossbar by default
> width = 16
>
> # A handful pipeline stages for each portion of the latency
> # contributions.
> frontend_latency = 3
> forward_latency = 4
> response_latency = 2
> snoop_response_latency = 4
>
> # In addition to the system interconnect, we typically also have one
> # or more on-chip I/O crossbars. Note that at some point we might want
> # to also define an off-chip I/O crossbar such as PCIe.
> class IOXBar(NoncoherentXBar):
> # 128-bit crossbar by default
> width = 16
>
> # Assume a simpler datapath than a coherent crossbar, incuring
> # less pipeline stages for decision making and forwarding of
> # requests.
> frontend_latency = 2
> forward_latency = 1
> response_latency = 2