1# Copyright (c) 2012, 2015, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.objects.System import System
43from m5.params import *
44from m5.proxy import *
45from m5.SimObject import SimObject
46
| 1# Copyright (c) 2012, 2015, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from m5.objects.System import System
43from m5.params import *
44from m5.proxy import *
45from m5.SimObject import SimObject
46
|
50 type = 'BaseXBar'
51 abstract = True
52 cxx_header = "mem/xbar.hh"
53
54 slave = VectorSlavePort("Vector port for connecting masters")
55 master = VectorMasterPort("Vector port for connecting slaves")
56
57 # Latencies governing the time taken for the variuos paths a
58 # packet has through the crossbar. Note that the crossbar itself
59 # does not add the latency due to assumptions in the coherency
60 # mechanism. Instead the latency is annotated on the packet and
61 # left to the neighbouring modules.
62 #
63 # A request incurs the frontend latency, possibly snoop filter
64 # lookup latency, and forward latency. A response incurs the
65 # response latency. Frontend latency encompasses arbitration and
66 # deciding what to do when a request arrives. the forward latency
67 # is the latency involved once a decision is made to forward the
68 # request. The response latency, is similar to the forward
69 # latency, but for responses rather than requests.
70 frontend_latency = Param.Cycles("Frontend latency")
71 forward_latency = Param.Cycles("Forward latency")
72 response_latency = Param.Cycles("Response latency")
73
74 # Width governing the throughput of the crossbar
75 width = Param.Unsigned("Datapath width per port (bytes)")
76
77 # The default port can be left unconnected, or be used to connect
78 # a default slave port
79 default = MasterPort("Port for connecting an optional default slave")
80
81 # The default port can be used unconditionally, or based on
82 # address range, in which case it may overlap with other
83 # ports. The default range is always checked first, thus creating
84 # a two-level hierarchical lookup. This is useful e.g. for the PCI
85 # xbar configuration.
86 use_default_range = Param.Bool(False, "Perform address mapping for " \
87 "the default port")
88
89class NoncoherentXBar(BaseXBar):
90 type = 'NoncoherentXBar'
91 cxx_header = "mem/noncoherent_xbar.hh"
92
93class CoherentXBar(BaseXBar):
94 type = 'CoherentXBar'
95 cxx_header = "mem/coherent_xbar.hh"
96
97 # The coherent crossbar additionally has snoop responses that are
98 # forwarded after a specific latency.
99 snoop_response_latency = Param.Cycles("Snoop response latency")
100
101 # An optional snoop filter
102 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
103
104 # Determine how this crossbar handles packets where caches have
105 # already committed to responding, by establishing if the crossbar
106 # is the point of coherency or not.
107 point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
108 "point of coherency")
109
110 # Specify whether this crossbar is the point of unification.
111 point_of_unification = Param.Bool(False, "Consider this crossbar the " \
112 "point of unification")
113
114 system = Param.System(Parent.any, "System that the crossbar belongs to.")
115
116class SnoopFilter(SimObject):
117 type = 'SnoopFilter'
118 cxx_header = "mem/snoop_filter.hh"
119
120 # Lookup latency of the snoop filter, added to requests that pass
121 # through a coherent crossbar.
122 lookup_latency = Param.Cycles(1, "Lookup latency")
123
124 system = Param.System(Parent.any, "System that the crossbar belongs to.")
125
126 # Sanity check on max capacity to track, adjust if needed.
127 max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
128
129# We use a coherent crossbar to connect multiple masters to the L2
130# caches. Normally this crossbar would be part of the cache itself.
131class L2XBar(CoherentXBar):
132 # 256-bit crossbar by default
133 width = 32
134
135 # Assume that most of this is covered by the cache latencies, with
136 # no more than a single pipeline stage for any packet.
137 frontend_latency = 1
138 forward_latency = 0
139 response_latency = 1
140 snoop_response_latency = 1
141
142 # Use a snoop-filter by default, and set the latency to zero as
143 # the lookup is assumed to overlap with the frontend latency of
144 # the crossbar
145 snoop_filter = SnoopFilter(lookup_latency = 0)
146
147 # This specialisation of the coherent crossbar is to be considered
148 # the point of unification, it connects the dcache and the icache
149 # to the first level of unified cache.
150 point_of_unification = True
151
152# One of the key coherent crossbar instances is the system
153# interconnect, tying together the CPU clusters, GPUs, and any I/O
154# coherent masters, and DRAM controllers.
155class SystemXBar(CoherentXBar):
156 # 128-bit crossbar by default
157 width = 16
158
159 # A handful pipeline stages for each portion of the latency
160 # contributions.
161 frontend_latency = 3
162 forward_latency = 4
163 response_latency = 2
164 snoop_response_latency = 4
165
166 # Use a snoop-filter by default
167 snoop_filter = SnoopFilter(lookup_latency = 1)
168
169 # This specialisation of the coherent crossbar is to be considered
170 # the point of coherency, as there are no (coherent) downstream
171 # caches.
172 point_of_coherency = True
173
174 # This specialisation of the coherent crossbar is to be considered
175 # the point of unification, it connects the dcache and the icache
176 # to the first level of unified cache. This is needed for systems
177 # without caches where the SystemXBar is also the point of
178 # unification.
179 point_of_unification = True
180
181# In addition to the system interconnect, we typically also have one
182# or more on-chip I/O crossbars. Note that at some point we might want
183# to also define an off-chip I/O crossbar such as PCIe.
184class IOXBar(NoncoherentXBar):
185 # 128-bit crossbar by default
186 width = 16
187
188 # Assume a simpler datapath than a coherent crossbar, incuring
189 # less pipeline stages for decision making and forwarding of
190 # requests.
191 frontend_latency = 2
192 forward_latency = 1
193 response_latency = 2
| 50 type = 'BaseXBar'
51 abstract = True
52 cxx_header = "mem/xbar.hh"
53
54 slave = VectorSlavePort("Vector port for connecting masters")
55 master = VectorMasterPort("Vector port for connecting slaves")
56
57 # Latencies governing the time taken for the variuos paths a
58 # packet has through the crossbar. Note that the crossbar itself
59 # does not add the latency due to assumptions in the coherency
60 # mechanism. Instead the latency is annotated on the packet and
61 # left to the neighbouring modules.
62 #
63 # A request incurs the frontend latency, possibly snoop filter
64 # lookup latency, and forward latency. A response incurs the
65 # response latency. Frontend latency encompasses arbitration and
66 # deciding what to do when a request arrives. the forward latency
67 # is the latency involved once a decision is made to forward the
68 # request. The response latency, is similar to the forward
69 # latency, but for responses rather than requests.
70 frontend_latency = Param.Cycles("Frontend latency")
71 forward_latency = Param.Cycles("Forward latency")
72 response_latency = Param.Cycles("Response latency")
73
74 # Width governing the throughput of the crossbar
75 width = Param.Unsigned("Datapath width per port (bytes)")
76
77 # The default port can be left unconnected, or be used to connect
78 # a default slave port
79 default = MasterPort("Port for connecting an optional default slave")
80
81 # The default port can be used unconditionally, or based on
82 # address range, in which case it may overlap with other
83 # ports. The default range is always checked first, thus creating
84 # a two-level hierarchical lookup. This is useful e.g. for the PCI
85 # xbar configuration.
86 use_default_range = Param.Bool(False, "Perform address mapping for " \
87 "the default port")
88
89class NoncoherentXBar(BaseXBar):
90 type = 'NoncoherentXBar'
91 cxx_header = "mem/noncoherent_xbar.hh"
92
93class CoherentXBar(BaseXBar):
94 type = 'CoherentXBar'
95 cxx_header = "mem/coherent_xbar.hh"
96
97 # The coherent crossbar additionally has snoop responses that are
98 # forwarded after a specific latency.
99 snoop_response_latency = Param.Cycles("Snoop response latency")
100
101 # An optional snoop filter
102 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
103
104 # Determine how this crossbar handles packets where caches have
105 # already committed to responding, by establishing if the crossbar
106 # is the point of coherency or not.
107 point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
108 "point of coherency")
109
110 # Specify whether this crossbar is the point of unification.
111 point_of_unification = Param.Bool(False, "Consider this crossbar the " \
112 "point of unification")
113
114 system = Param.System(Parent.any, "System that the crossbar belongs to.")
115
116class SnoopFilter(SimObject):
117 type = 'SnoopFilter'
118 cxx_header = "mem/snoop_filter.hh"
119
120 # Lookup latency of the snoop filter, added to requests that pass
121 # through a coherent crossbar.
122 lookup_latency = Param.Cycles(1, "Lookup latency")
123
124 system = Param.System(Parent.any, "System that the crossbar belongs to.")
125
126 # Sanity check on max capacity to track, adjust if needed.
127 max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
128
129# We use a coherent crossbar to connect multiple masters to the L2
130# caches. Normally this crossbar would be part of the cache itself.
131class L2XBar(CoherentXBar):
132 # 256-bit crossbar by default
133 width = 32
134
135 # Assume that most of this is covered by the cache latencies, with
136 # no more than a single pipeline stage for any packet.
137 frontend_latency = 1
138 forward_latency = 0
139 response_latency = 1
140 snoop_response_latency = 1
141
142 # Use a snoop-filter by default, and set the latency to zero as
143 # the lookup is assumed to overlap with the frontend latency of
144 # the crossbar
145 snoop_filter = SnoopFilter(lookup_latency = 0)
146
147 # This specialisation of the coherent crossbar is to be considered
148 # the point of unification, it connects the dcache and the icache
149 # to the first level of unified cache.
150 point_of_unification = True
151
152# One of the key coherent crossbar instances is the system
153# interconnect, tying together the CPU clusters, GPUs, and any I/O
154# coherent masters, and DRAM controllers.
155class SystemXBar(CoherentXBar):
156 # 128-bit crossbar by default
157 width = 16
158
159 # A handful pipeline stages for each portion of the latency
160 # contributions.
161 frontend_latency = 3
162 forward_latency = 4
163 response_latency = 2
164 snoop_response_latency = 4
165
166 # Use a snoop-filter by default
167 snoop_filter = SnoopFilter(lookup_latency = 1)
168
169 # This specialisation of the coherent crossbar is to be considered
170 # the point of coherency, as there are no (coherent) downstream
171 # caches.
172 point_of_coherency = True
173
174 # This specialisation of the coherent crossbar is to be considered
175 # the point of unification, it connects the dcache and the icache
176 # to the first level of unified cache. This is needed for systems
177 # without caches where the SystemXBar is also the point of
178 # unification.
179 point_of_unification = True
180
181# In addition to the system interconnect, we typically also have one
182# or more on-chip I/O crossbars. Note that at some point we might want
183# to also define an off-chip I/O crossbar such as PCIe.
184class IOXBar(NoncoherentXBar):
185 # 128-bit crossbar by default
186 width = 16
187
188 # Assume a simpler datapath than a coherent crossbar, incuring
189 # less pipeline stages for decision making and forwarding of
190 # requests.
191 frontend_latency = 2
192 forward_latency = 1
193 response_latency = 2
|