1# Copyright (c) 2012, 2015 ARM Limited
| 1# Copyright (c) 2012, 2015, 2017 ARM Limited
|
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from MemObject import MemObject
43from System import System
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47
48class BaseXBar(MemObject):
49 type = 'BaseXBar'
50 abstract = True
51 cxx_header = "mem/xbar.hh"
52
53 slave = VectorSlavePort("Vector port for connecting masters")
54 master = VectorMasterPort("Vector port for connecting slaves")
55
56 # Latencies governing the time taken for the variuos paths a
57 # packet has through the crossbar. Note that the crossbar itself
58 # does not add the latency due to assumptions in the coherency
59 # mechanism. Instead the latency is annotated on the packet and
60 # left to the neighbouring modules.
61 #
62 # A request incurs the frontend latency, possibly snoop filter
63 # lookup latency, and forward latency. A response incurs the
64 # response latency. Frontend latency encompasses arbitration and
65 # deciding what to do when a request arrives. the forward latency
66 # is the latency involved once a decision is made to forward the
67 # request. The response latency, is similar to the forward
68 # latency, but for responses rather than requests.
69 frontend_latency = Param.Cycles("Frontend latency")
70 forward_latency = Param.Cycles("Forward latency")
71 response_latency = Param.Cycles("Response latency")
72
73 # Width governing the throughput of the crossbar
74 width = Param.Unsigned("Datapath width per port (bytes)")
75
76 # The default port can be left unconnected, or be used to connect
77 # a default slave port
78 default = MasterPort("Port for connecting an optional default slave")
79
80 # The default port can be used unconditionally, or based on
81 # address range, in which case it may overlap with other
82 # ports. The default range is always checked first, thus creating
83 # a two-level hierarchical lookup. This is useful e.g. for the PCI
84 # xbar configuration.
85 use_default_range = Param.Bool(False, "Perform address mapping for " \
86 "the default port")
87
88class NoncoherentXBar(BaseXBar):
89 type = 'NoncoherentXBar'
90 cxx_header = "mem/noncoherent_xbar.hh"
91
92class CoherentXBar(BaseXBar):
93 type = 'CoherentXBar'
94 cxx_header = "mem/coherent_xbar.hh"
95
96 # The coherent crossbar additionally has snoop responses that are
97 # forwarded after a specific latency.
98 snoop_response_latency = Param.Cycles("Snoop response latency")
99
100 # An optional snoop filter
101 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
102
103 # Determine how this crossbar handles packets where caches have
104 # already committed to responding, by establishing if the crossbar
105 # is the point of coherency or not.
106 point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
107 "point of coherency")
108
| 2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from MemObject import MemObject
43from System import System
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47
48class BaseXBar(MemObject):
49 type = 'BaseXBar'
50 abstract = True
51 cxx_header = "mem/xbar.hh"
52
53 slave = VectorSlavePort("Vector port for connecting masters")
54 master = VectorMasterPort("Vector port for connecting slaves")
55
56 # Latencies governing the time taken for the variuos paths a
57 # packet has through the crossbar. Note that the crossbar itself
58 # does not add the latency due to assumptions in the coherency
59 # mechanism. Instead the latency is annotated on the packet and
60 # left to the neighbouring modules.
61 #
62 # A request incurs the frontend latency, possibly snoop filter
63 # lookup latency, and forward latency. A response incurs the
64 # response latency. Frontend latency encompasses arbitration and
65 # deciding what to do when a request arrives. the forward latency
66 # is the latency involved once a decision is made to forward the
67 # request. The response latency, is similar to the forward
68 # latency, but for responses rather than requests.
69 frontend_latency = Param.Cycles("Frontend latency")
70 forward_latency = Param.Cycles("Forward latency")
71 response_latency = Param.Cycles("Response latency")
72
73 # Width governing the throughput of the crossbar
74 width = Param.Unsigned("Datapath width per port (bytes)")
75
76 # The default port can be left unconnected, or be used to connect
77 # a default slave port
78 default = MasterPort("Port for connecting an optional default slave")
79
80 # The default port can be used unconditionally, or based on
81 # address range, in which case it may overlap with other
82 # ports. The default range is always checked first, thus creating
83 # a two-level hierarchical lookup. This is useful e.g. for the PCI
84 # xbar configuration.
85 use_default_range = Param.Bool(False, "Perform address mapping for " \
86 "the default port")
87
88class NoncoherentXBar(BaseXBar):
89 type = 'NoncoherentXBar'
90 cxx_header = "mem/noncoherent_xbar.hh"
91
92class CoherentXBar(BaseXBar):
93 type = 'CoherentXBar'
94 cxx_header = "mem/coherent_xbar.hh"
95
96 # The coherent crossbar additionally has snoop responses that are
97 # forwarded after a specific latency.
98 snoop_response_latency = Param.Cycles("Snoop response latency")
99
100 # An optional snoop filter
101 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
102
103 # Determine how this crossbar handles packets where caches have
104 # already committed to responding, by establishing if the crossbar
105 # is the point of coherency or not.
106 point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
107 "point of coherency")
108
|
| 109 # Specify whether this crossbar is the point of unification.
110 point_of_unification = Param.Bool(False, "Consider this crossbar the " \
111 "point of unification")
112
|
109 system = Param.System(Parent.any, "System that the crossbar belongs to.")
110
111class SnoopFilter(SimObject):
112 type = 'SnoopFilter'
113 cxx_header = "mem/snoop_filter.hh"
114
115 # Lookup latency of the snoop filter, added to requests that pass
116 # through a coherent crossbar.
117 lookup_latency = Param.Cycles(1, "Lookup latency")
118
119 system = Param.System(Parent.any, "System that the crossbar belongs to.")
120
121 # Sanity check on max capacity to track, adjust if needed.
122 max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
123
124# We use a coherent crossbar to connect multiple masters to the L2
125# caches. Normally this crossbar would be part of the cache itself.
126class L2XBar(CoherentXBar):
127 # 256-bit crossbar by default
128 width = 32
129
130 # Assume that most of this is covered by the cache latencies, with
131 # no more than a single pipeline stage for any packet.
132 frontend_latency = 1
133 forward_latency = 0
134 response_latency = 1
135 snoop_response_latency = 1
136
137 # Use a snoop-filter by default, and set the latency to zero as
138 # the lookup is assumed to overlap with the frontend latency of
139 # the crossbar
140 snoop_filter = SnoopFilter(lookup_latency = 0)
141
| 113 system = Param.System(Parent.any, "System that the crossbar belongs to.")
114
115class SnoopFilter(SimObject):
116 type = 'SnoopFilter'
117 cxx_header = "mem/snoop_filter.hh"
118
119 # Lookup latency of the snoop filter, added to requests that pass
120 # through a coherent crossbar.
121 lookup_latency = Param.Cycles(1, "Lookup latency")
122
123 system = Param.System(Parent.any, "System that the crossbar belongs to.")
124
125 # Sanity check on max capacity to track, adjust if needed.
126 max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
127
128# We use a coherent crossbar to connect multiple masters to the L2
129# caches. Normally this crossbar would be part of the cache itself.
130class L2XBar(CoherentXBar):
131 # 256-bit crossbar by default
132 width = 32
133
134 # Assume that most of this is covered by the cache latencies, with
135 # no more than a single pipeline stage for any packet.
136 frontend_latency = 1
137 forward_latency = 0
138 response_latency = 1
139 snoop_response_latency = 1
140
141 # Use a snoop-filter by default, and set the latency to zero as
142 # the lookup is assumed to overlap with the frontend latency of
143 # the crossbar
144 snoop_filter = SnoopFilter(lookup_latency = 0)
145
|
| 146 # This specialisation of the coherent crossbar is to be considered
147 # the point of unification, it connects the dcache and the icache
148 # to the first level of unified cache.
149 point_of_unification = True
150
|
142# One of the key coherent crossbar instances is the system
143# interconnect, tying together the CPU clusters, GPUs, and any I/O
144# coherent masters, and DRAM controllers.
145class SystemXBar(CoherentXBar):
146 # 128-bit crossbar by default
147 width = 16
148
149 # A handful pipeline stages for each portion of the latency
150 # contributions.
151 frontend_latency = 3
152 forward_latency = 4
153 response_latency = 2
154 snoop_response_latency = 4
155
156 # Use a snoop-filter by default
157 snoop_filter = SnoopFilter(lookup_latency = 1)
158
159 # This specialisation of the coherent crossbar is to be considered
160 # the point of coherency, as there are no (coherent) downstream
161 # caches.
162 point_of_coherency = True
163
| 151# One of the key coherent crossbar instances is the system
152# interconnect, tying together the CPU clusters, GPUs, and any I/O
153# coherent masters, and DRAM controllers.
154class SystemXBar(CoherentXBar):
155 # 128-bit crossbar by default
156 width = 16
157
158 # A handful pipeline stages for each portion of the latency
159 # contributions.
160 frontend_latency = 3
161 forward_latency = 4
162 response_latency = 2
163 snoop_response_latency = 4
164
165 # Use a snoop-filter by default
166 snoop_filter = SnoopFilter(lookup_latency = 1)
167
168 # This specialisation of the coherent crossbar is to be considered
169 # the point of coherency, as there are no (coherent) downstream
170 # caches.
171 point_of_coherency = True
172
|
| 173 # This specialisation of the coherent crossbar is to be considered
174 # the point of unification, it connects the dcache and the icache
175 # to the first level of unified cache. This is needed for systems
176 # without caches where the SystemXBar is also the point of
177 # unification.
178 point_of_unification = True
179
|
164# In addition to the system interconnect, we typically also have one
165# or more on-chip I/O crossbars. Note that at some point we might want
166# to also define an off-chip I/O crossbar such as PCIe.
167class IOXBar(NoncoherentXBar):
168 # 128-bit crossbar by default
169 width = 16
170
171 # Assume a simpler datapath than a coherent crossbar, incuring
172 # less pipeline stages for decision making and forwarding of
173 # requests.
174 frontend_latency = 2
175 forward_latency = 1
176 response_latency = 2
| 180# In addition to the system interconnect, we typically also have one
181# or more on-chip I/O crossbars. Note that at some point we might want
182# to also define an off-chip I/O crossbar such as PCIe.
183class IOXBar(NoncoherentXBar):
184 # 128-bit crossbar by default
185 width = 16
186
187 # Assume a simpler datapath than a coherent crossbar, incuring
188 # less pipeline stages for decision making and forwarding of
189 # requests.
190 frontend_latency = 2
191 forward_latency = 1
192 response_latency = 2
|