XBar.py (10720:67b3e74de9ae) XBar.py (11132:fbd597034299)
1# Copyright (c) 2012, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from MemObject import MemObject
43from System import System
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47
48class BaseXBar(MemObject):
49 type = 'BaseXBar'
50 abstract = True
51 cxx_header = "mem/xbar.hh"
52
53 slave = VectorSlavePort("Vector port for connecting masters")
54 master = VectorMasterPort("Vector port for connecting slaves")
55
56 # Latencies governing the time taken for the variuos paths a
57 # packet has through the crossbar. Note that the crossbar itself
58 # does not add the latency due to assumptions in the coherency
59 # mechanism. Instead the latency is annotated on the packet and
60 # left to the neighbouring modules.
61 #
62 # A request incurs the frontend latency, possibly snoop filter
63 # lookup latency, and forward latency. A response incurs the
64 # response latency. Frontend latency encompasses arbitration and
65 # deciding what to do when a request arrives. the forward latency
66 # is the latency involved once a decision is made to forward the
67 # request. The response latency, is similar to the forward
68 # latency, but for responses rather than requests.
69 frontend_latency = Param.Cycles("Frontend latency")
70 forward_latency = Param.Cycles("Forward latency")
71 response_latency = Param.Cycles("Response latency")
72
73 # Width governing the throughput of the crossbar
74 width = Param.Unsigned("Datapath width per port (bytes)")
75
76 # The default port can be left unconnected, or be used to connect
77 # a default slave port
78 default = MasterPort("Port for connecting an optional default slave")
79
80 # The default port can be used unconditionally, or based on
81 # address range, in which case it may overlap with other
82 # ports. The default range is always checked first, thus creating
83 # a two-level hierarchical lookup. This is useful e.g. for the PCI
84 # xbar configuration.
85 use_default_range = Param.Bool(False, "Perform address mapping for " \
86 "the default port")
87
88class NoncoherentXBar(BaseXBar):
89 type = 'NoncoherentXBar'
90 cxx_header = "mem/noncoherent_xbar.hh"
91
92class CoherentXBar(BaseXBar):
93 type = 'CoherentXBar'
94 cxx_header = "mem/coherent_xbar.hh"
95
96 # The coherent crossbar additionally has snoop responses that are
97 # forwarded after a specific latency.
98 snoop_response_latency = Param.Cycles("Snoop response latency")
99
100 # An optional snoop filter
101 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
102
103 system = Param.System(Parent.any, "System that the crossbar belongs to.")
104
105class SnoopFilter(SimObject):
106 type = 'SnoopFilter'
107 cxx_header = "mem/snoop_filter.hh"
108
109 # Lookup latency of the snoop filter, added to requests that pass
110 # through a coherent crossbar.
111 lookup_latency = Param.Cycles(1, "Lookup latency")
112
113 system = Param.System(Parent.any, "System that the crossbar belongs to.")
114
1# Copyright (c) 2012, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40# Andreas Hansson
41
42from MemObject import MemObject
43from System import System
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47
48class BaseXBar(MemObject):
49 type = 'BaseXBar'
50 abstract = True
51 cxx_header = "mem/xbar.hh"
52
53 slave = VectorSlavePort("Vector port for connecting masters")
54 master = VectorMasterPort("Vector port for connecting slaves")
55
56 # Latencies governing the time taken for the variuos paths a
57 # packet has through the crossbar. Note that the crossbar itself
58 # does not add the latency due to assumptions in the coherency
59 # mechanism. Instead the latency is annotated on the packet and
60 # left to the neighbouring modules.
61 #
62 # A request incurs the frontend latency, possibly snoop filter
63 # lookup latency, and forward latency. A response incurs the
64 # response latency. Frontend latency encompasses arbitration and
65 # deciding what to do when a request arrives. the forward latency
66 # is the latency involved once a decision is made to forward the
67 # request. The response latency, is similar to the forward
68 # latency, but for responses rather than requests.
69 frontend_latency = Param.Cycles("Frontend latency")
70 forward_latency = Param.Cycles("Forward latency")
71 response_latency = Param.Cycles("Response latency")
72
73 # Width governing the throughput of the crossbar
74 width = Param.Unsigned("Datapath width per port (bytes)")
75
76 # The default port can be left unconnected, or be used to connect
77 # a default slave port
78 default = MasterPort("Port for connecting an optional default slave")
79
80 # The default port can be used unconditionally, or based on
81 # address range, in which case it may overlap with other
82 # ports. The default range is always checked first, thus creating
83 # a two-level hierarchical lookup. This is useful e.g. for the PCI
84 # xbar configuration.
85 use_default_range = Param.Bool(False, "Perform address mapping for " \
86 "the default port")
87
88class NoncoherentXBar(BaseXBar):
89 type = 'NoncoherentXBar'
90 cxx_header = "mem/noncoherent_xbar.hh"
91
92class CoherentXBar(BaseXBar):
93 type = 'CoherentXBar'
94 cxx_header = "mem/coherent_xbar.hh"
95
96 # The coherent crossbar additionally has snoop responses that are
97 # forwarded after a specific latency.
98 snoop_response_latency = Param.Cycles("Snoop response latency")
99
100 # An optional snoop filter
101 snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
102
103 system = Param.System(Parent.any, "System that the crossbar belongs to.")
104
105class SnoopFilter(SimObject):
106 type = 'SnoopFilter'
107 cxx_header = "mem/snoop_filter.hh"
108
109 # Lookup latency of the snoop filter, added to requests that pass
110 # through a coherent crossbar.
111 lookup_latency = Param.Cycles(1, "Lookup latency")
112
113 system = Param.System(Parent.any, "System that the crossbar belongs to.")
114
115 # Sanity check on max capacity to track, adjust if needed.
116 max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
117
115# We use a coherent crossbar to connect multiple masters to the L2
116# caches. Normally this crossbar would be part of the cache itself.
117class L2XBar(CoherentXBar):
118 # 256-bit crossbar by default
119 width = 32
120
121 # Assume that most of this is covered by the cache latencies, with
122 # no more than a single pipeline stage for any packet.
123 frontend_latency = 1
124 forward_latency = 0
125 response_latency = 1
126 snoop_response_latency = 1
127
118# We use a coherent crossbar to connect multiple masters to the L2
119# caches. Normally this crossbar would be part of the cache itself.
120class L2XBar(CoherentXBar):
121 # 256-bit crossbar by default
122 width = 32
123
124 # Assume that most of this is covered by the cache latencies, with
125 # no more than a single pipeline stage for any packet.
126 frontend_latency = 1
127 forward_latency = 0
128 response_latency = 1
129 snoop_response_latency = 1
130
131 # Use a snoop-filter by default, and set the latency to zero as
132 # the lookup is assumed to overlap with the frontend latency of
133 # the crossbar
134 snoop_filter = SnoopFilter(lookup_latency = 0)
135
128# One of the key coherent crossbar instances is the system
129# interconnect, tying together the CPU clusters, GPUs, and any I/O
130# coherent masters, and DRAM controllers.
131class SystemXBar(CoherentXBar):
132 # 128-bit crossbar by default
133 width = 16
134
135 # A handful pipeline stages for each portion of the latency
136 # contributions.
137 frontend_latency = 3
138 forward_latency = 4
139 response_latency = 2
140 snoop_response_latency = 4
141
142# In addition to the system interconnect, we typically also have one
143# or more on-chip I/O crossbars. Note that at some point we might want
144# to also define an off-chip I/O crossbar such as PCIe.
145class IOXBar(NoncoherentXBar):
146 # 128-bit crossbar by default
147 width = 16
148
149 # Assume a simpler datapath than a coherent crossbar, incuring
150 # less pipeline stages for decision making and forwarding of
151 # requests.
152 frontend_latency = 2
153 forward_latency = 1
154 response_latency = 2
136# One of the key coherent crossbar instances is the system
137# interconnect, tying together the CPU clusters, GPUs, and any I/O
138# coherent masters, and DRAM controllers.
139class SystemXBar(CoherentXBar):
140 # 128-bit crossbar by default
141 width = 16
142
143 # A handful pipeline stages for each portion of the latency
144 # contributions.
145 frontend_latency = 3
146 forward_latency = 4
147 response_latency = 2
148 snoop_response_latency = 4
149
150# In addition to the system interconnect, we typically also have one
151# or more on-chip I/O crossbars. Note that at some point we might want
152# to also define an off-chip I/O crossbar such as PCIe.
153class IOXBar(NoncoherentXBar):
154 # 128-bit crossbar by default
155 width = 16
156
157 # Assume a simpler datapath than a coherent crossbar, incuring
158 # less pipeline stages for decision making and forwarding of
159 # requests.
160 frontend_latency = 2
161 forward_latency = 1
162 response_latency = 2