SimpleMemory.py (9120:48eeef8a0997) | SimpleMemory.py (9228:bbdca4088834) |
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1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42from m5.params import * 43from AbstractMemory import * 44 45class SimpleMemory(AbstractMemory): 46 type = 'SimpleMemory' 47 port = SlavePort("Slave ports") 48 latency = Param.Latency('30ns', "Request to response latency") 49 latency_var = Param.Latency('0ns', "Request to response latency variance") | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42from m5.params import * 43from AbstractMemory import * 44 45class SimpleMemory(AbstractMemory): 46 type = 'SimpleMemory' 47 port = SlavePort("Slave ports") 48 latency = Param.Latency('30ns', "Request to response latency") 49 latency_var = Param.Latency('0ns', "Request to response latency variance") |
50 # The memory bandwidth limit default is set to 12.8GB/s which is 51 # representative of a x64 DDR3-1600 channel. 52 bandwidth = Param.MemoryBandwidth('12.8GB/s', 53 "Combined read and write bandwidth") |
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