| MemDelay.py (13665:9c7fe3811b88) | MemDelay.py (13892:0182a0601f66) |
|---|---|
| 1# Copyright (c) 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 22 unchanged lines hidden (view full) --- 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from m5.params import * | 1# Copyright (c) 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 22 unchanged lines hidden (view full) --- 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from m5.params import * |
| 39from m5.objects.MemObject import MemObject | 39from m5.objects.ClockedObject import ClockedObject |
| 40 | 40 |
| 41class MemDelay(MemObject): | 41class MemDelay(ClockedObject): |
| 42 type = 'MemDelay' 43 cxx_header = 'mem/mem_delay.hh' 44 abstract = True 45 46 master = MasterPort("Master port") 47 slave = SlavePort("Slave port") 48 49class SimpleMemDelay(MemDelay): 50 type = 'SimpleMemDelay' 51 cxx_header = 'mem/mem_delay.hh' 52 53 read_req = Param.Latency("0t", "Read request delay") 54 read_resp = Param.Latency("0t", "Read response delay") 55 56 write_req = Param.Latency("0t", "Write request delay") 57 write_resp = Param.Latency("0t", "Write response delay") | 42 type = 'MemDelay' 43 cxx_header = 'mem/mem_delay.hh' 44 abstract = True 45 46 master = MasterPort("Master port") 47 slave = SlavePort("Slave port") 48 49class SimpleMemDelay(MemDelay): 50 type = 'SimpleMemDelay' 51 cxx_header = 'mem/mem_delay.hh' 52 53 read_req = Param.Latency("0t", "Read request delay") 54 read_resp = Param.Latency("0t", "Read response delay") 55 56 write_req = Param.Latency("0t", "Write request delay") 57 write_resp = Param.Latency("0t", "Write response delay") |