1# Copyright (c) 2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Marco Elver
37
38from m5.objects.MemObject import MemObject
39from m5.SimObject import SimObject
40from m5.params import *
41from m5.proxy import *
42
43class MemChecker(SimObject):
44 type = 'MemChecker'
45 cxx_header = "mem/mem_checker.hh"
46
47class MemCheckerMonitor(MemObject):
48 type = 'MemCheckerMonitor'
49 cxx_header = "mem/mem_checker_monitor.hh"
50
51 # one port in each direction
52 master = MasterPort("Master port")
53 slave = SlavePort("Slave port")
54 cpu_side = SlavePort("Alias for slave")
55 mem_side = MasterPort("Alias for master")
56 warn_only = Param.Bool(False, "Warn about violations only")
57 memchecker = Param.MemChecker("Instance shared with other monitors")
58