| DRAMCtrl.py (12706:456304051464) | DRAMCtrl.py (12969:52de9d619ce6) |
|---|---|
| 1# Copyright (c) 2012-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42# Ani Udipi 43# Omar Naji 44# Matthias Jung 45# Erfan Azarkhish 46 47from m5.params import * 48from m5.proxy import * 49from AbstractMemory import * | 1# Copyright (c) 2012-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42# Ani Udipi 43# Omar Naji 44# Matthias Jung 45# Erfan Azarkhish 46 47from m5.params import * 48from m5.proxy import * 49from AbstractMemory import * |
| 50from QoSMemCtrl import * |
|
| 50 51# Enum for memory scheduling algorithms, currently First-Come 52# First-Served and a First-Row Hit then First-Come First-Served 53class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 54 55# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 56# channel, rank, bank, row and column, respectively, and going from 57# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are --- 6 unchanged lines hidden (view full) --- 64# close_adaptive. 65class PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 66 'close_adaptive'] 67 68# DRAMCtrl is a single-channel single-ported DRAM controller model 69# that aims to model the most important system-level performance 70# effects of a DRAM without getting into too much detail of the DRAM 71# itself. | 51 52# Enum for memory scheduling algorithms, currently First-Come 53# First-Served and a First-Row Hit then First-Come First-Served 54class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 55 56# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 57# channel, rank, bank, row and column, respectively, and going from 58# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are --- 6 unchanged lines hidden (view full) --- 65# close_adaptive. 66class PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 67 'close_adaptive'] 68 69# DRAMCtrl is a single-channel single-ported DRAM controller model 70# that aims to model the most important system-level performance 71# effects of a DRAM without getting into too much detail of the DRAM 72# itself. |
| 72class DRAMCtrl(AbstractMemory): | 73class DRAMCtrl(QoSMemCtrl): |
| 73 type = 'DRAMCtrl' 74 cxx_header = "mem/dram_ctrl.hh" 75 76 # single-ported on the system interface side, instantiate with a 77 # bus in front of the controller for multiple ports 78 port = SlavePort("Slave port") 79 80 # the basic configuration of the controller architecture, note --- 1116 unchanged lines hidden --- | 74 type = 'DRAMCtrl' 75 cxx_header = "mem/dram_ctrl.hh" 76 77 # single-ported on the system interface side, instantiate with a 78 # bus in front of the controller for multiple ports 79 port = SlavePort("Slave port") 80 81 # the basic configuration of the controller architecture, note --- 1116 unchanged lines hidden --- |