| DRAMCtrl.py (12516:483fc7339fb1) | DRAMCtrl.py (12706:456304051464) |
|---|---|
| 1# Copyright (c) 2012-2016 ARM Limited | 1# Copyright (c) 2012-2018 ARM Limited |
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 30 unchanged lines hidden (view full) --- 40# 41# Authors: Andreas Hansson 42# Ani Udipi 43# Omar Naji 44# Matthias Jung 45# Erfan Azarkhish 46 47from m5.params import * | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 30 unchanged lines hidden (view full) --- 40# 41# Authors: Andreas Hansson 42# Ani Udipi 43# Omar Naji 44# Matthias Jung 45# Erfan Azarkhish 46 47from m5.params import * |
| 48from m5.proxy import * |
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| 48from AbstractMemory import * 49 50# Enum for memory scheduling algorithms, currently First-Come 51# First-Served and a First-Row Hit then First-Come First-Served 52class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 53 54# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 55# channel, rank, bank, row and column, respectively, and going from --- 122 unchanged lines hidden (view full) --- 178 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 179 180 # CAS-to-CAS delay for bursts to the same bank group 181 # only utilized with bank group architectures; set to 0 for default case 182 # tBURST is equivalent to tCCD_S; no explicit parameter required 183 # for CAS-to-CAS delay for bursts to different bank groups 184 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 185 | 49from AbstractMemory import * 50 51# Enum for memory scheduling algorithms, currently First-Come 52# First-Served and a First-Row Hit then First-Come First-Served 53class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 54 55# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 56# channel, rank, bank, row and column, respectively, and going from --- 122 unchanged lines hidden (view full) --- 179 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 180 181 # CAS-to-CAS delay for bursts to the same bank group 182 # only utilized with bank group architectures; set to 0 for default case 183 # tBURST is equivalent to tCCD_S; no explicit parameter required 184 # for CAS-to-CAS delay for bursts to different bank groups 185 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 186 |
| 187 # Write-to-Write delay for bursts to the same bank group 188 # only utilized with bank group architectures; set to 0 for default case 189 # This will be used to enable different same bank group delays 190 # for writes versus reads 191 tCCD_L_WR = Param.Latency(Self.tCCD_L, 192 "Same bank group Write to Write delay") 193 |
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| 186 # time taken to complete one refresh cycle (N rows in all banks) 187 tRFC = Param.Latency("Refresh cycle time") 188 189 # refresh command interval, how often a "ref" command needs 190 # to be sent. It is 7.8 us for a 64ms refresh requirement 191 tREFI = Param.Latency("Refresh command interval") 192 193 # write-to-read, same rank turnaround penalty --- 995 unchanged lines hidden --- | 194 # time taken to complete one refresh cycle (N rows in all banks) 195 tRFC = Param.Latency("Refresh cycle time") 196 197 # refresh command interval, how often a "ref" command needs 198 # to be sent. It is 7.8 us for a 64ms refresh requirement 199 tREFI = Param.Latency("Refresh command interval") 200 201 # write-to-read, same rank turnaround penalty --- 995 unchanged lines hidden --- |