DRAMCtrl.py (11672:55276af429ed) | DRAMCtrl.py (11673:9f3ccf96bb5a) |
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1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 356 unchanged lines hidden (view full) --- 365 tRTW = '2.5ns' 366 367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 368 tCS = '2.5ns' 369 370 # <=85C, half for >85C 371 tREFI = '7.8us' 372 | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 356 unchanged lines hidden (view full) --- 365 tRTW = '2.5ns' 366 367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 368 tCS = '2.5ns' 369 370 # <=85C, half for >85C 371 tREFI = '7.8us' 372 |
373 # active powerdown and precharge powerdown exit time 374 tXP = '6ns' 375 376 # self refresh exit time 377 tXS = '270ns' 378 |
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373 # Current values from datasheet 374 IDD0 = '75mA' 375 IDD2N = '50mA' 376 IDD3N = '57mA' 377 IDD4W = '165mA' 378 IDD4R = '187mA' 379 IDD5 = '220mA' 380 VDD = '1.5V' --- 205 unchanged lines hidden (view full) --- 586 tRTW = '1.666ns' 587 588 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 589 tCS = '1.666ns' 590 591 # <=85C, half for >85C 592 tREFI = '7.8us' 593 | 379 # Current values from datasheet 380 IDD0 = '75mA' 381 IDD2N = '50mA' 382 IDD3N = '57mA' 383 IDD4W = '165mA' 384 IDD4R = '187mA' 385 IDD5 = '220mA' 386 VDD = '1.5V' --- 205 unchanged lines hidden (view full) --- 592 tRTW = '1.666ns' 593 594 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 595 tCS = '1.666ns' 596 597 # <=85C, half for >85C 598 tREFI = '7.8us' 599 |
600 # active powerdown and precharge powerdown exit time 601 tXP = '6ns' 602 603 # self refresh exit time 604 tXS = '120ns' 605 |
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594 # Current values from datasheet 595 IDD0 = '70mA' 596 IDD02 = '4.6mA' 597 IDD2N = '50mA' 598 IDD3N = '67mA' 599 IDD3N2 = '3mA' 600 IDD4W = '302mA' 601 IDD4R = '230mA' --- 52 unchanged lines hidden (view full) --- 654 # Requests larger than 32 bytes are broken down into multiple requests 655 # in the controller 656 tBURST = '7.5ns' 657 658 # LPDDR2-S4, 4 Gbit 659 tRFC = '130ns' 660 tREFI = '3.9us' 661 | 606 # Current values from datasheet 607 IDD0 = '70mA' 608 IDD02 = '4.6mA' 609 IDD2N = '50mA' 610 IDD3N = '67mA' 611 IDD3N2 = '3mA' 612 IDD4W = '302mA' 613 IDD4R = '230mA' --- 52 unchanged lines hidden (view full) --- 666 # Requests larger than 32 bytes are broken down into multiple requests 667 # in the controller 668 tBURST = '7.5ns' 669 670 # LPDDR2-S4, 4 Gbit 671 tRFC = '130ns' 672 tREFI = '3.9us' 673 |
674 # active powerdown and precharge powerdown exit time 675 tXP = '7.5ns' 676 677 # self refresh exit time 678 tXS = '140ns' 679 |
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662 # Irrespective of speed grade, tWTR is 7.5 ns 663 tWTR = '7.5ns' 664 665 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 666 tRTW = '3.75ns' 667 668 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 669 tCS = '3.75ns' --- 140 unchanged lines hidden (view full) --- 810 # Requests larger than 32 bytes are broken down into multiple requests 811 # in the controller 812 tBURST = '5ns' 813 814 # LPDDR3, 4 Gb 815 tRFC = '130ns' 816 tREFI = '3.9us' 817 | 680 # Irrespective of speed grade, tWTR is 7.5 ns 681 tWTR = '7.5ns' 682 683 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 684 tRTW = '3.75ns' 685 686 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 687 tCS = '3.75ns' --- 140 unchanged lines hidden (view full) --- 828 # Requests larger than 32 bytes are broken down into multiple requests 829 # in the controller 830 tBURST = '5ns' 831 832 # LPDDR3, 4 Gb 833 tRFC = '130ns' 834 tREFI = '3.9us' 835 |
836 # active powerdown and precharge powerdown exit time 837 tXP = '7.5ns' 838 839 # self refresh exit time 840 tXS = '140ns' 841 |
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818 # Irrespective of speed grade, tWTR is 7.5 ns 819 tWTR = '7.5ns' 820 821 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 822 tRTW = '2.5ns' 823 824 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 825 tCS = '2.5ns' --- 226 unchanged lines hidden (view full) --- 1052 # use HBM1 4Gb value as a starting point 1053 tRFC = '260ns' 1054 1055 # start with tRFC + tXP -> 160ns + 8ns = 168ns 1056 tXS = '268ns' 1057 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 1058 tCS = '2ns' 1059 tREFI = '3.9us' | 842 # Irrespective of speed grade, tWTR is 7.5 ns 843 tWTR = '7.5ns' 844 845 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 846 tRTW = '2.5ns' 847 848 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 849 tCS = '2.5ns' --- 226 unchanged lines hidden (view full) --- 1076 # use HBM1 4Gb value as a starting point 1077 tRFC = '260ns' 1078 1079 # start with tRFC + tXP -> 160ns + 8ns = 168ns 1080 tXS = '268ns' 1081 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 1082 tCS = '2ns' 1083 tREFI = '3.9us' |
1084 1085 # active powerdown and precharge powerdown exit time 1086 tXP = '10ns' 1087 1088 # self refresh exit time 1089 tXS = '65ns' |
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