DRAMCtrl.py (10891:d958fc5f4a00) DRAMCtrl.py (11120:eef83ecab5bf)
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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907 tWTR = '5ns'
908
909 # Read-to-Precharge 2 CK
910 tRTP = '2ns'
911
912 # Assume 2 cycles
913 tRTW = '2ns'
914
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 898 unchanged lines hidden (view full) ---

907 tWTR = '5ns'
908
909 # Read-to-Precharge 2 CK
910 tRTP = '2ns'
911
912 # Assume 2 cycles
913 tRTW = '2ns'
914
915# A single HBM x128 interface (one command and address bus), with
916# default timings based on data publically released
917# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
918# IDD measurement values, and by extrapolating data from other classes.
919# Architecture values based on published HBM spec
920# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
921class HBM_1000_4H_x128(DRAMCtrl):
922 # HBM gen1 supports up to 8 128-bit physical channels
923 # Configuration defines a single channel, with the capacity
924 # set to (full_ stack_capacity / 8) based on 2Gb dies
925 # To use all 8 channels, set 'channels' parameter to 8 in
926 # system configuration
927
928 # 128-bit interface legacy mode
929 device_bus_width = 128
930
931 # HBM supports BL4 and BL2 (legacy mode only)
932 burst_length = 4
933
934 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
935 # with 8 channels, 128MB per channel
936 device_size = '128MB'
937
938 device_rowbuffer_size = '2kB'
939
940 # 1x128 configuration
941 devices_per_rank = 1
942
943 # HBM does not have a CS pin; set rank to 1
944 ranks_per_channel = 1
945
946 # HBM has 8 or 16 banks depending on capacity
947 # 2Gb dies have 8 banks
948 banks_per_rank = 8
949
950 # depending on frequency, bank groups may be required
951 # will always have 4 bank groups when enabled
952 # current specifications do not define the minimum frequency for
953 # bank group architecture
954 # setting bank_groups_per_rank to 0 to disable until range is defined
955 bank_groups_per_rank = 0
956
957 # 500 MHz for 1Gbps DDR data rate
958 tCK = '2ns'
959
960 # use values from IDD measurement in JEDEC spec
961 # use tRP value for tRCD and tCL similar to other classes
962 tRP = '15ns'
963 tRCD = '15ns'
964 tCL = '15ns'
965 tRAS = '33ns'
966
967 # BL2 and BL4 supported, default to BL4
968 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
969 tBURST = '4ns'
970
971 # value for 2Gb device from JEDEC spec
972 tRFC = '160ns'
973
974 # value for 2Gb device from JEDEC spec
975 tREFI = '3.9us'
976
977 # extrapolate the following from LPDDR configs, using ns values
978 # to minimize burst length, prefetch differences
979 tWR = '18ns'
980 tRTP = '7.5ns'
981 tWTR = '10ns'
982
983 # start with 2 cycles turnaround, similar to other memory classes
984 # could be more with variations across the stack
985 tRTW = '4ns'
986
987 # single rank device, set to 0
988 tCS = '0ns'
989
990 # from MemCon example, tRRD is 4ns with 2ns tCK
991 tRRD = '4ns'
992
993 # from MemCon example, tFAW is 30ns with 2ns tCK
994 tXAW = '30ns'
995 activation_limit = 4
996
997 # 4tCK
998 tXP = '8ns'
999
1000 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1001 tXS = '168ns'
1002
1003# A single HBM x64 interface (one command and address bus), with
1004# default timings based on HBM gen1 and data publically released
1005# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1006# Note: This defines a pseudo-channel with a unique controller
1007# instantiated per pseudo-channel
1008# Stay at same IO rate (1Gbps) to maintain timing relationship with
1009# HBM gen1 class (HBM_1000_4H_x128) where possible
1010class HBM_1000_4H_x64(HBM_1000_4H_x128):
1011 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1012 # Configuration defines a single pseudo channel, with the capacity
1013 # set to (full_ stack_capacity / 16) based on 8Gb dies
1014 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1015 # system configuration
1016
1017 # 64-bit pseudo-channle interface
1018 device_bus_width = 64
1019
1020 # HBM pseudo-channel only supports BL4
1021 burst_length = 4
1022
1023 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1024 # with 16 channels, 256MB per channel
1025 device_size = '256MB'
1026
1027 # page size is halved with pseudo-channel; maintaining the same same number
1028 # of rows per pseudo-channel with 2X banks across 2 channels
1029 device_rowbuffer_size = '1kB'
1030
1031 # HBM has 8 or 16 banks depending on capacity
1032 # Starting with 4Gb dies, 16 banks are defined
1033 banks_per_rank = 16
1034
1035 # reset tRFC for larger, 8Gb device
1036 # use HBM1 4Gb value as a starting point
1037 tRFC = '260ns'
1038
1039 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1040 tXS = '268ns'
915 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
916 tCS = '2ns'
917 tREFI = '3.9us'
1041 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1042 tCS = '2ns'
1043 tREFI = '3.9us'