DRAMCtrl.py (10536:aa97958ce2aa) DRAMCtrl.py (10561:e1a853349529)
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 722 unchanged lines hidden (view full) ---

731 IDD4W = '2mA'
732 IDD4W2 = '190mA'
733 IDD4R = '2mA'
734 IDD4R2 = '230mA'
735 IDD5 = '28mA'
736 IDD52 = '150mA'
737 VDD = '1.8V'
738 VDD2 = '1.2V'
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 722 unchanged lines hidden (view full) ---

731 IDD4W = '2mA'
732 IDD4W2 = '190mA'
733 IDD4R = '2mA'
734 IDD4R2 = '230mA'
735 IDD5 = '28mA'
736 IDD52 = '150mA'
737 VDD = '1.8V'
738 VDD2 = '1.2V'
739
740# A single GDDR5 x64 interface, with
741# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
742# H5GQ1H24AFR) in a 2x32 configuration.
743class GDDR5_4000_x64(DRAMCtrl):
744 # size of device
745 device_size = '128MB'
746
747 # 2x32 configuration, 1 device with a 32-bit interface
748 device_bus_width = 32
749
750 # GDDR5 is a BL8 device
751 burst_length = 8
752
753 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
754 device_rowbuffer_size = '256B'
755
756 # 2x32 configuration, so 2 devices
757 devices_per_rank = 2
758
759 # assume single rank
760 ranks_per_channel = 1
761
762 # GDDR5 has 4 bank groups
763 bank_groups_per_rank = 4
764
765 # GDDR5 has 16 banks with 4 bank groups
766 banks_per_rank = 16
767
768 # 1000 MHz
769 tCK = '1ns'
770
771 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
772 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
773 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
774 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
775 # With bank group architectures, tBURST represents the CAS-to-CAS
776 # delay for bursts to different bank groups (tCCD_S)
777 tBURST = '2ns'
778
779 # @1000MHz data rate, tCCD_L is 3 CK
780 # CAS-to-CAS delay for bursts to the same bank group
781 # tBURST is equivalent to tCCD_S; no explicit parameter required
782 # for CAS-to-CAS delay for bursts to different bank groups
783 tCCD_L = '3ns';
784
785 tRCD = '12ns'
786
787 # tCL is not directly found in datasheet and assumed equal tRCD
788 tCL = '12ns'
789
790 tRP = '12ns'
791 tRAS = '28ns'
792
793 # RRD_S (different bank group)
794 # RRD_S is 5.5 ns in datasheet.
795 # rounded to the next multiple of tCK
796 tRRD = '6ns'
797
798 # RRD_L (same bank group)
799 # RRD_L is 5.5 ns in datasheet.
800 # rounded to the next multiple of tCK
801 tRRD_L = '6ns'
802
803 tXAW = '23ns'
804
805 # tXAW < 4 x tRRD.
806 # Therefore, activation limit is set to 0
807 activation_limit = 0
808
809 tRFC = '65ns'
810 tWR = '12ns'
811
812 # Here using the average of WTR_S and WTR_L
813 tWTR = '5ns'
814
815 # Read-to-Precharge 2 CK
816 tRTP = '2ns'
817
818 # Assume 2 cycles
819 tRTW = '2ns'
820
821 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
822 tCS = '2ns'
823 tREFI = '3.9us'