DRAMCtrl.py (10430:f958ccec628f) | DRAMCtrl.py (10489:99d59caa4c8f) |
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1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 82 unchanged lines hidden (view full) --- 91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 93 page_policy = Param.PageManage('open_adaptive', "Page management policy") 94 95 # enforce a limit on the number of accesses per row 96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 97 "closing"); 98 | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 82 unchanged lines hidden (view full) --- 91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 93 page_policy = Param.PageManage('open_adaptive', "Page management policy") 94 95 # enforce a limit on the number of accesses per row 96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 97 "closing"); 98 |
99 # size of DRAM Chip in Bytes 100 device_size = Param.MemorySize("Size of DRAM chip") 101 |
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99 # pipeline latency of the controller and PHY, split into a 100 # frontend part and a backend part, with reads and writes serviced 101 # by the queues only seeing the frontend contribution, and reads 102 # serviced by the memory seeing the sum of the two 103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 104 static_backend_latency = Param.Latency("10ns", "Static backend latency") 105 106 # the physical organisation of the DRAM --- 193 unchanged lines hidden (view full) --- 300 301 # Second voltage range defined by some DRAMs 302 VDD2 = Param.Voltage("0V", "2nd Voltage Range") 303 304# A single DDR3-1600 x64 channel (one command and address bus), with 305# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 306# an 8x8 configuration. 307class DDR3_1600_x64(DRAMCtrl): | 102 # pipeline latency of the controller and PHY, split into a 103 # frontend part and a backend part, with reads and writes serviced 104 # by the queues only seeing the frontend contribution, and reads 105 # serviced by the memory seeing the sum of the two 106 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 107 static_backend_latency = Param.Latency("10ns", "Static backend latency") 108 109 # the physical organisation of the DRAM --- 193 unchanged lines hidden (view full) --- 303 304 # Second voltage range defined by some DRAMs 305 VDD2 = Param.Voltage("0V", "2nd Voltage Range") 306 307# A single DDR3-1600 x64 channel (one command and address bus), with 308# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 309# an 8x8 configuration. 310class DDR3_1600_x64(DRAMCtrl): |
311 # size of device in bytes 312 device_size = '512MB' 313 |
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308 # 8x8 configuration, 8 devices each with an 8-bit interface 309 device_bus_width = 8 310 311 # DDR3 is a BL8 device 312 burst_length = 8 313 314 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 315 device_rowbuffer_size = '1kB' --- 76 unchanged lines hidden (view full) --- 392 IDD4R = '191mA' 393 IDD5 = '250mA' 394 VDD = '1.5V' 395 396# A single DDR4-2400 x64 channel (one command and address bus), with 397# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) 398# in an 8x8 configuration. 399class DDR4_2400_x64(DRAMCtrl): | 314 # 8x8 configuration, 8 devices each with an 8-bit interface 315 device_bus_width = 8 316 317 # DDR3 is a BL8 device 318 burst_length = 8 319 320 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 321 device_rowbuffer_size = '1kB' --- 76 unchanged lines hidden (view full) --- 398 IDD4R = '191mA' 399 IDD5 = '250mA' 400 VDD = '1.5V' 401 402# A single DDR4-2400 x64 channel (one command and address bus), with 403# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) 404# in an 8x8 configuration. 405class DDR4_2400_x64(DRAMCtrl): |
406 # size of device 407 device_size = '512MB' 408 |
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400 # 8x8 configuration, 8 devices each with an 8-bit interface 401 device_bus_width = 8 402 403 # DDR4 is a BL8 device 404 burst_length = 8 405 406 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 407 device_rowbuffer_size = '1kB' --- 75 unchanged lines hidden (view full) --- 483 484# A single LPDDR2-S4 x32 interface (one command/address bus), with 485# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 486# in a 1x32 configuration. 487class LPDDR2_S4_1066_x32(DRAMCtrl): 488 # No DLL in LPDDR2 489 dll = False 490 | 409 # 8x8 configuration, 8 devices each with an 8-bit interface 410 device_bus_width = 8 411 412 # DDR4 is a BL8 device 413 burst_length = 8 414 415 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 416 device_rowbuffer_size = '1kB' --- 75 unchanged lines hidden (view full) --- 492 493# A single LPDDR2-S4 x32 interface (one command/address bus), with 494# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 495# in a 1x32 configuration. 496class LPDDR2_S4_1066_x32(DRAMCtrl): 497 # No DLL in LPDDR2 498 dll = False 499 |
500 # size of device 501 device_size = '512MB' 502 |
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491 # 1x32 configuration, 1 device with a 32-bit interface 492 device_bus_width = 32 493 494 # LPDDR2_S4 is a BL4 and BL8 device 495 burst_length = 8 496 497 # Each device has a page (row buffer) size of 1KB 498 # (this depends on the memory density) --- 68 unchanged lines hidden (view full) --- 567 VDD2 = '1.2V' 568 569# A single WideIO x128 interface (one command and address bus), with 570# default timings based on an estimated WIO-200 8 Gbit part. 571class WideIO_200_x128(DRAMCtrl): 572 # No DLL for WideIO 573 dll = False 574 | 503 # 1x32 configuration, 1 device with a 32-bit interface 504 device_bus_width = 32 505 506 # LPDDR2_S4 is a BL4 and BL8 device 507 burst_length = 8 508 509 # Each device has a page (row buffer) size of 1KB 510 # (this depends on the memory density) --- 68 unchanged lines hidden (view full) --- 579 VDD2 = '1.2V' 580 581# A single WideIO x128 interface (one command and address bus), with 582# default timings based on an estimated WIO-200 8 Gbit part. 583class WideIO_200_x128(DRAMCtrl): 584 # No DLL for WideIO 585 dll = False 586 |
587 # size of device 588 device_size = '1024MB' 589 |
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575 # 1x128 configuration, 1 device with a 128-bit interface 576 device_bus_width = 128 577 578 # This is a BL4 device 579 burst_length = 4 580 581 # Each device has a page (row buffer) size of 4KB 582 # (this depends on the memory density) --- 50 unchanged lines hidden (view full) --- 633 634# A single LPDDR3 x32 interface (one command/address bus), with 635# default timings based on a LPDDR3-1600 4 Gbit part (Micron 636# EDF8132A1MC) in a 1x32 configuration. 637class LPDDR3_1600_x32(DRAMCtrl): 638 # No DLL for LPDDR3 639 dll = False 640 | 590 # 1x128 configuration, 1 device with a 128-bit interface 591 device_bus_width = 128 592 593 # This is a BL4 device 594 burst_length = 4 595 596 # Each device has a page (row buffer) size of 4KB 597 # (this depends on the memory density) --- 50 unchanged lines hidden (view full) --- 648 649# A single LPDDR3 x32 interface (one command/address bus), with 650# default timings based on a LPDDR3-1600 4 Gbit part (Micron 651# EDF8132A1MC) in a 1x32 configuration. 652class LPDDR3_1600_x32(DRAMCtrl): 653 # No DLL for LPDDR3 654 dll = False 655 |
656 # size of device 657 device_size = '512MB' 658 |
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641 # 1x32 configuration, 1 device with a 32-bit interface 642 device_bus_width = 32 643 644 # LPDDR3 is a BL8 device 645 burst_length = 8 646 647 # Each device has a page (row buffer) size of 4KB 648 device_rowbuffer_size = '4kB' --- 69 unchanged lines hidden --- | 659 # 1x32 configuration, 1 device with a 32-bit interface 660 device_bus_width = 32 661 662 # LPDDR3 is a BL8 device 663 burst_length = 8 664 665 # Each device has a page (row buffer) size of 4KB 666 device_rowbuffer_size = '4kB' --- 69 unchanged lines hidden --- |