DRAMCtrl.py (10429:025a459edb87) DRAMCtrl.py (10430:f958ccec628f)
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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117 # update per memory class when bank group architecture is supported
118 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
119 banks_per_rank = Param.Unsigned("Number of banks per rank")
120 # only used for the address mapping as the controller by
121 # construction is a single channel and multiple controllers have
122 # to be instantiated for a multi-channel configuration
123 channels = Param.Unsigned(1, "Number of channels")
124
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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117 # update per memory class when bank group architecture is supported
118 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
119 banks_per_rank = Param.Unsigned("Number of banks per rank")
120 # only used for the address mapping as the controller by
121 # construction is a single channel and multiple controllers have
122 # to be instantiated for a multi-channel configuration
123 channels = Param.Unsigned(1, "Number of channels")
124
125 # For power modelling we need to know if the DRAM has a DLL or not
126 dll = Param.Bool(True, "DRAM has DLL or not")
127
128 # DRAMPower provides in addition to the core power, the possibility to
129 # include RD/WR termination and IO power. This calculation assumes some
130 # default values. The integration of DRAMPower with gem5 does not include
131 # IO and RD/WR termination power by default. This might be added as an
132 # additional feature in the future.
133
125 # timing behaviour and constraints - all in nanoseconds
126
127 # the base clock period of the DRAM
128 tCK = Param.Latency("Clock period")
129
130 # the amount of time in nanoseconds from issuing an activate command
131 # to the data being available in the row buffer for a read/write
132 tRCD = Param.Latency("RAS to CAS delay")

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188 # only utilized with bank group architectures; set to 0 for default case
189 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
190
191 # time window in which a maximum number of activates are allowed
192 # to take place, set to 0 to disable
193 tXAW = Param.Latency("X activation window")
194 activation_limit = Param.Unsigned("Max number of activates in window")
195
134 # timing behaviour and constraints - all in nanoseconds
135
136 # the base clock period of the DRAM
137 tCK = Param.Latency("Clock period")
138
139 # the amount of time in nanoseconds from issuing an activate command
140 # to the data being available in the row buffer for a read/write
141 tRCD = Param.Latency("RAS to CAS delay")

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197 # only utilized with bank group architectures; set to 0 for default case
198 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
199
200 # time window in which a maximum number of activates are allowed
201 # to take place, set to 0 to disable
202 tXAW = Param.Latency("X activation window")
203 activation_limit = Param.Unsigned("Max number of activates in window")
204
205 # time to exit power-down mode
206 # Exit power-down to next valid command delay
207 tXP = Param.Latency("0ns", "Power-up Delay")
208
209 # Exit Powerdown to commands requiring a locked DLL
210 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
211
212 # time to exit self-refresh mode
213 tXS = Param.Latency("0ns", "Self-refresh exit latency")
214
215 # time to exit self-refresh mode with locked DLL
216 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
217
196 # Currently rolled into other params
197 ######################################################################
198
199 # tRC - assumed to be tRAS + tRP
200
218 # Currently rolled into other params
219 ######################################################################
220
221 # tRC - assumed to be tRAS + tRP
222
223 # Power Behaviour and Constraints
224 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
225 # defined as VDD and VDD2. Each current is defined for each voltage domain
226 # separately. For example, current IDD0 is active-precharge current for
227 # voltage domain VDD and current IDD02 is active-precharge current for
228 # voltage domain VDD2.
229 # By default all currents are set to 0mA. Users who are only interested in
230 # the performance of DRAMs can leave them at 0.
231
232 # Operating 1 Bank Active-Precharge current
233 IDD0 = Param.Current("0mA", "Active precharge current")
234
235 # Operating 1 Bank Active-Precharge current multiple voltage Range
236 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
237
238 # Precharge Power-down Current: Slow exit
239 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
240
241 # Precharge Power-down Current: Slow exit multiple voltage Range
242 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
243
244 # Precharge Power-down Current: Fast exit
245 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
246
247 # Precharge Power-down Current: Fast exit multiple voltage Range
248 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
249
250 # Precharge Standby current
251 IDD2N = Param.Current("0mA", "Precharge Standby current")
252
253 # Precharge Standby current multiple voltage range
254 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
255
256 # Active Power-down current: slow exit
257 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
258
259 # Active Power-down current: slow exit multiple voltage range
260 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
261
262 # Active Power-down current : fast exit
263 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
264
265 # Active Power-down current : fast exit multiple voltage range
266 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
267
268 # Active Standby current
269 IDD3N = Param.Current("0mA", "Active Standby current")
270
271 # Active Standby current multiple voltage range
272 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
273
274 # Burst Read Operating Current
275 IDD4R = Param.Current("0mA", "READ current")
276
277 # Burst Read Operating Current multiple voltage range
278 IDD4R2 = Param.Current("0mA", "READ current VDD2")
279
280 # Burst Write Operating Current
281 IDD4W = Param.Current("0mA", "WRITE current")
282
283 # Burst Write Operating Current multiple voltage range
284 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
285
286 # Refresh Current
287 IDD5 = Param.Current("0mA", "Refresh current")
288
289 # Refresh Current multiple voltage range
290 IDD52 = Param.Current("0mA", "Refresh current VDD2")
291
292 # Self-Refresh Current
293 IDD6 = Param.Current("0mA", "Self-refresh Current")
294
295 # Self-Refresh Current multiple voltage range
296 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
297
298 # Main voltage range of the DRAM
299 VDD = Param.Voltage("0V", "Main Voltage Range")
300
301 # Second voltage range defined by some DRAMs
302 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
303
201# A single DDR3-1600 x64 channel (one command and address bus), with
202# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
304# A single DDR3-1600 x64 channel (one command and address bus), with
305# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
203# an 8x8 configuration, amounting to 4 Gbyte of memory.
306# an 8x8 configuration.
204class DDR3_1600_x64(DRAMCtrl):
205 # 8x8 configuration, 8 devices each with an 8-bit interface
206 device_bus_width = 8
207
208 # DDR3 is a BL8 device
209 burst_length = 8
210
211 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)

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248 tRTW = '2.5ns'
249
250 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
251 tCS = '2.5ns'
252
253 # <=85C, half for >85C
254 tREFI = '7.8us'
255
307class DDR3_1600_x64(DRAMCtrl):
308 # 8x8 configuration, 8 devices each with an 8-bit interface
309 device_bus_width = 8
310
311 # DDR3 is a BL8 device
312 burst_length = 8
313
314 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)

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351 tRTW = '2.5ns'
352
353 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
354 tCS = '2.5ns'
355
356 # <=85C, half for >85C
357 tREFI = '7.8us'
358
359 # Current values from datasheet
360 IDD0 = '75mA'
361 IDD2N = '50mA'
362 IDD3N = '57mA'
363 IDD4W = '165mA'
364 IDD4R = '187mA'
365 IDD5 = '220mA'
366 VDD = '1.5V'
367
256# A single DDR3-2133 x64 channel refining a selected subset of the
257# options for the DDR-1600 configuration, based on the same DDR3-1600
258# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
259# consistent across the two configurations.
260class DDR3_2133_x64(DDR3_1600_x64):
261 # 1066 MHz
262 tCK = '0.938ns'
263
264 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
265 tBURST = '3.752ns'
266
267 # DDR3-2133 14-14-14
268 tRCD = '13.09ns'
269 tCL = '13.09ns'
270 tRP = '13.09ns'
271 tRAS = '33ns'
272 tRRD = '5ns'
273 tXAW = '25ns'
274
368# A single DDR3-2133 x64 channel refining a selected subset of the
369# options for the DDR-1600 configuration, based on the same DDR3-1600
370# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
371# consistent across the two configurations.
372class DDR3_2133_x64(DDR3_1600_x64):
373 # 1066 MHz
374 tCK = '0.938ns'
375
376 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
377 tBURST = '3.752ns'
378
379 # DDR3-2133 14-14-14
380 tRCD = '13.09ns'
381 tCL = '13.09ns'
382 tRP = '13.09ns'
383 tRAS = '33ns'
384 tRRD = '5ns'
385 tXAW = '25ns'
386
387 # Current values from datasheet
388 IDD0 = '70mA'
389 IDD2N = '37mA'
390 IDD3N = '44mA'
391 IDD4W = '157mA'
392 IDD4R = '191mA'
393 IDD5 = '250mA'
394 VDD = '1.5V'
395
275# A single DDR4-2400 x64 channel (one command and address bus), with
396# A single DDR4-2400 x64 channel (one command and address bus), with
276# timings based on a DDR4-2400 4 Gbit datasheet (Samsung K4A4G085WD)
277# in an 8x8 configuration, amounting to 4 Gbyte of memory.
397# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
398# in an 8x8 configuration.
278class DDR4_2400_x64(DRAMCtrl):
279 # 8x8 configuration, 8 devices each with an 8-bit interface
280 device_bus_width = 8
281
282 # DDR4 is a BL8 device
283 burst_length = 8
284
285 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
286 device_rowbuffer_size = '1kB'
287
288 # 8x8 configuration, so 8 devices
289 devices_per_rank = 8
290
399class DDR4_2400_x64(DRAMCtrl):
400 # 8x8 configuration, 8 devices each with an 8-bit interface
401 device_bus_width = 8
402
403 # DDR4 is a BL8 device
404 burst_length = 8
405
406 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
407 device_rowbuffer_size = '1kB'
408
409 # 8x8 configuration, so 8 devices
410 devices_per_rank = 8
411
291 # Use a single rank
292 ranks_per_channel = 1
412 # Match our DDR3 configurations which is dual rank
413 ranks_per_channel = 2
293
294 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
295 # Set to 4 for x4, x8 case
296 bank_groups_per_rank = 4
297
298 # DDR4 has 16 banks (4 bank groups) in all
299 # configurations. Currently we do not capture the additional
300 # constraints incurred by the bank groups

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324 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
325 tRRD = '3.3ns'
326
327 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
328 tRRD_L = '4.9ns';
329
330 tXAW = '21ns'
331 activation_limit = 4
414
415 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
416 # Set to 4 for x4, x8 case
417 bank_groups_per_rank = 4
418
419 # DDR4 has 16 banks (4 bank groups) in all
420 # configurations. Currently we do not capture the additional
421 # constraints incurred by the bank groups

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445 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
446 tRRD = '3.3ns'
447
448 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
449 tRRD_L = '4.9ns';
450
451 tXAW = '21ns'
452 activation_limit = 4
332 tRFC = '260ns'
453 tRFC = '350ns'
333
334 tWR = '15ns'
335
336 # Here using the average of WTR_S and WTR_L
337 tWTR = '5ns'
338
339 # Greater of 4 CK or 7.5 ns
340 tRTP = '7.5ns'
341
342 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
343 tRTW = '1.666ns'
344
345 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
346 tCS = '1.666ns'
347
348 # <=85C, half for >85C
349 tREFI = '7.8us'
350
454
455 tWR = '15ns'
456
457 # Here using the average of WTR_S and WTR_L
458 tWTR = '5ns'
459
460 # Greater of 4 CK or 7.5 ns
461 tRTP = '7.5ns'
462
463 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
464 tRTW = '1.666ns'
465
466 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
467 tCS = '1.666ns'
468
469 # <=85C, half for >85C
470 tREFI = '7.8us'
471
472 # Current values from datasheet
473 IDD0 = '64mA'
474 IDD02 = '4mA'
475 IDD2N = '50mA'
476 IDD3N = '67mA'
477 IDD3N2 = '3mA'
478 IDD4W = '180mA'
479 IDD4R = '160mA'
480 IDD5 = '192mA'
481 VDD = '1.2V'
482 VDD2 = '2.5V'
483
351# A single LPDDR2-S4 x32 interface (one command/address bus), with
484# A single LPDDR2-S4 x32 interface (one command/address bus), with
352# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
353# configuration.
485# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
486# in a 1x32 configuration.
354class LPDDR2_S4_1066_x32(DRAMCtrl):
487class LPDDR2_S4_1066_x32(DRAMCtrl):
488 # No DLL in LPDDR2
489 dll = False
490
355 # 1x32 configuration, 1 device with a 32-bit interface
356 device_bus_width = 32
357
358 # LPDDR2_S4 is a BL4 and BL8 device
359 burst_length = 8
360
361 # Each device has a page (row buffer) size of 1KB
362 # (this depends on the memory density)

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381 tCL = '15ns'
382
383 # Pre-charge one bank 15 ns (all banks 18 ns)
384 tRP = '15ns'
385
386 tRAS = '42ns'
387 tWR = '15ns'
388
491 # 1x32 configuration, 1 device with a 32-bit interface
492 device_bus_width = 32
493
494 # LPDDR2_S4 is a BL4 and BL8 device
495 burst_length = 8
496
497 # Each device has a page (row buffer) size of 1KB
498 # (this depends on the memory density)

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517 tCL = '15ns'
518
519 # Pre-charge one bank 15 ns (all banks 18 ns)
520 tRP = '15ns'
521
522 tRAS = '42ns'
523 tWR = '15ns'
524
389 # 6 CK read to precharge delay
390 tRTP = '11.256ns'
525 tRTP = '7.5ns'
391
392 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
393 # Note this is a BL8 DDR device.
394 # Requests larger than 32 bytes are broken down into multiple requests
395 # in the controller
396 tBURST = '7.5ns'
397
398 # LPDDR2-S4, 4 Gbit

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410
411 # Activate to activate irrespective of density and speed grade
412 tRRD = '10.0ns'
413
414 # Irrespective of density, tFAW is 50 ns
415 tXAW = '50ns'
416 activation_limit = 4
417
526
527 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
528 # Note this is a BL8 DDR device.
529 # Requests larger than 32 bytes are broken down into multiple requests
530 # in the controller
531 tBURST = '7.5ns'
532
533 # LPDDR2-S4, 4 Gbit

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545
546 # Activate to activate irrespective of density and speed grade
547 tRRD = '10.0ns'
548
549 # Irrespective of density, tFAW is 50 ns
550 tXAW = '50ns'
551 activation_limit = 4
552
553 # Current values from datasheet
554 IDD0 = '15mA'
555 IDD02 = '70mA'
556 IDD2N = '2mA'
557 IDD2N2 = '30mA'
558 IDD3N = '2.5mA'
559 IDD3N2 = '30mA'
560 IDD4W = '10mA'
561 IDD4W2 = '190mA'
562 IDD4R = '3mA'
563 IDD4R2 = '220mA'
564 IDD5 = '40mA'
565 IDD52 = '150mA'
566 VDD = '1.8V'
567 VDD2 = '1.2V'
568
418# A single WideIO x128 interface (one command and address bus), with
419# default timings based on an estimated WIO-200 8 Gbit part.
420class WideIO_200_x128(DRAMCtrl):
569# A single WideIO x128 interface (one command and address bus), with
570# default timings based on an estimated WIO-200 8 Gbit part.
571class WideIO_200_x128(DRAMCtrl):
572 # No DLL for WideIO
573 dll = False
574
421 # 1x128 configuration, 1 device with a 128-bit interface
422 device_bus_width = 128
423
424 # This is a BL4 device
425 burst_length = 4
426
427 # Each device has a page (row buffer) size of 4KB
428 # (this depends on the memory density)

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470
471 # Activate to activate irrespective of density and speed grade
472 tRRD = '10.0ns'
473
474 # Two instead of four activation window
475 tXAW = '50ns'
476 activation_limit = 2
477
575 # 1x128 configuration, 1 device with a 128-bit interface
576 device_bus_width = 128
577
578 # This is a BL4 device
579 burst_length = 4
580
581 # Each device has a page (row buffer) size of 4KB
582 # (this depends on the memory density)

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624
625 # Activate to activate irrespective of density and speed grade
626 tRRD = '10.0ns'
627
628 # Two instead of four activation window
629 tXAW = '50ns'
630 activation_limit = 2
631
632 # The WideIO specification does not provide current information
633
478# A single LPDDR3 x32 interface (one command/address bus), with
634# A single LPDDR3 x32 interface (one command/address bus), with
479# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
480# configuration
635# default timings based on a LPDDR3-1600 4 Gbit part (Micron
636# EDF8132A1MC) in a 1x32 configuration.
481class LPDDR3_1600_x32(DRAMCtrl):
637class LPDDR3_1600_x32(DRAMCtrl):
638 # No DLL for LPDDR3
639 dll = False
640
482 # 1x32 configuration, 1 device with a 32-bit interface
483 device_bus_width = 32
484
485 # LPDDR3 is a BL8 device
486 burst_length = 8
487
488 # Each device has a page (row buffer) size of 4KB
489 device_rowbuffer_size = '4kB'
490
491 # 1x32 configuration, so 1 device
492 devices_per_rank = 1
493
641 # 1x32 configuration, 1 device with a 32-bit interface
642 device_bus_width = 32
643
644 # LPDDR3 is a BL8 device
645 burst_length = 8
646
647 # Each device has a page (row buffer) size of 4KB
648 device_rowbuffer_size = '4kB'
649
650 # 1x32 configuration, so 1 device
651 devices_per_rank = 1
652
494 # Use a single rank
653 # Technically the datasheet is a dual-rank package, but for
654 # comparison with the LPDDR2 config we stick to a single rank
495 ranks_per_channel = 1
496
497 # LPDDR3 has 8 banks in all configurations
498 banks_per_rank = 8
499
500 # 800 MHz
501 tCK = '1.25ns'
502
655 ranks_per_channel = 1
656
657 # LPDDR3 has 8 banks in all configurations
658 banks_per_rank = 8
659
660 # 800 MHz
661 tCK = '1.25ns'
662
503 # Fixed at 15 ns
504 tRCD = '15ns'
663 tRCD = '18ns'
505
506 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
507 tCL = '15ns'
508
509 tRAS = '42ns'
510 tWR = '15ns'
511
512 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
513 tRTP = '7.5ns'
514
664
665 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
666 tCL = '15ns'
667
668 tRAS = '42ns'
669 tWR = '15ns'
670
671 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
672 tRTP = '7.5ns'
673
515 # Pre-charge one bank 15 ns (all banks 18 ns)
516 tRP = '15ns'
674 # Pre-charge one bank 18 ns (all banks 21 ns)
675 tRP = '18ns'
517
518 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
519 # Note this is a BL8 DDR device.
520 # Requests larger than 32 bytes are broken down into multiple requests
521 # in the controller
522 tBURST = '5ns'
523
524 # LPDDR3, 4 Gb

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535 tCS = '2.5ns'
536
537 # Activate to activate irrespective of density and speed grade
538 tRRD = '10.0ns'
539
540 # Irrespective of size, tFAW is 50 ns
541 tXAW = '50ns'
542 activation_limit = 4
676
677 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
678 # Note this is a BL8 DDR device.
679 # Requests larger than 32 bytes are broken down into multiple requests
680 # in the controller
681 tBURST = '5ns'
682
683 # LPDDR3, 4 Gb

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694 tCS = '2.5ns'
695
696 # Activate to activate irrespective of density and speed grade
697 tRRD = '10.0ns'
698
699 # Irrespective of size, tFAW is 50 ns
700 tXAW = '50ns'
701 activation_limit = 4
702
703 # Current values from datasheet
704 IDD0 = '8mA'
705 IDD02 = '60mA'
706 IDD2N = '0.8mA'
707 IDD2N2 = '26mA'
708 IDD3N = '2mA'
709 IDD3N2 = '34mA'
710 IDD4W = '2mA'
711 IDD4W2 = '190mA'
712 IDD4R = '2mA'
713 IDD4R2 = '230mA'
714 IDD5 = '28mA'
715 IDD52 = '150mA'
716 VDD = '1.8V'
717 VDD2 = '1.2V'