| DRAMCtrl.py (10394:70cfafa17653) | DRAMCtrl.py (10429:025a459edb87) |
|---|---|
| 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 334 unchanged lines hidden (view full) --- 343 tRTW = '1.666ns' 344 345 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 346 tCS = '1.666ns' 347 348 # <=85C, half for >85C 349 tREFI = '7.8us' 350 | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 334 unchanged lines hidden (view full) --- 343 tRTW = '1.666ns' 344 345 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 346 tCS = '1.666ns' 347 348 # <=85C, half for >85C 349 tREFI = '7.8us' 350 |
| 351# A single DDR3 x64 interface (one command and address bus), with 352# default timings based on DDR3-1333 4 Gbit parts in an 8x8 353# configuration, which would amount to 4 GByte of memory. This 354# configuration is primarily for comparing with DRAMSim2, and all the 355# parameters except ranks_per_channel are based on the DRAMSim2 config 356# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 357# to be manually set, depending on size of the memory to be 358# simulated. By default DRAMSim2 has 2048MB of memory with a single 359# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 360class DDR3_1333_x64_DRAMSim2(DRAMCtrl): 361 # 8x8 configuration, 8 devices each with an 8-bit interface 362 device_bus_width = 8 363 364 # DDR3 is a BL8 device 365 burst_length = 8 366 367 # Each device has a page (row buffer) size of 1KB 368 # (this depends on the memory density) 369 device_rowbuffer_size = '1kB' 370 371 # 8x8 configuration, so 8 devices 372 devices_per_rank = 8 373 374 # Use two ranks 375 ranks_per_channel = 2 376 377 # DDR3 has 8 banks in all configurations 378 banks_per_rank = 8 379 380 # 666 MHs 381 tCK = '1.5ns' 382 383 tRCD = '15ns' 384 tCL = '15ns' 385 tRP = '15ns' 386 tRAS = '36ns' 387 tWR = '15ns' 388 tRTP = '7.5ns' 389 390 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 391 # Note this is a BL8 DDR device. 392 tBURST = '6ns' 393 394 tRFC = '160ns' 395 396 # DDR3, <=85C, half for >85C 397 tREFI = '7.8us' 398 399 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 400 tWTR = '7.5ns' 401 402 # Default same rank rd-to-wr bus turnaround to 2 CK, @666.66 MHz = 3 ns 403 tRTW = '3ns' 404 405 # Default different rank bus delay to 2 CK, @666.66 MHz = 3 ns 406 tCS = '3ns' 407 408 tRRD = '6.0ns' 409 410 tXAW = '30ns' 411 activation_limit = 4 412 413 | |
| 414# A single LPDDR2-S4 x32 interface (one command/address bus), with 415# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 416# configuration. 417class LPDDR2_S4_1066_x32(DRAMCtrl): 418 # 1x32 configuration, 1 device with a 32-bit interface 419 device_bus_width = 32 420 421 # LPDDR2_S4 is a BL4 and BL8 device --- 184 unchanged lines hidden --- | 351# A single LPDDR2-S4 x32 interface (one command/address bus), with 352# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 353# configuration. 354class LPDDR2_S4_1066_x32(DRAMCtrl): 355 # 1x32 configuration, 1 device with a 32-bit interface 356 device_bus_width = 32 357 358 # LPDDR2_S4 is a BL4 and BL8 device --- 184 unchanged lines hidden --- |