| DRAMCtrl.py (10216:52c869140fc2) | DRAMCtrl.py (10217:baf8754fd5be) |
|---|---|
| 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 161 unchanged lines hidden (view full) --- 170 tXAW = Param.Latency("X activation window") 171 activation_limit = Param.Unsigned("Max number of activates in window") 172 173 # Currently rolled into other params 174 ###################################################################### 175 176 # tRC - assumed to be tRAS + tRP 177 | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 161 unchanged lines hidden (view full) --- 170 tXAW = Param.Latency("X activation window") 171 activation_limit = Param.Unsigned("Max number of activates in window") 172 173 # Currently rolled into other params 174 ###################################################################### 175 176 # tRC - assumed to be tRAS + tRP 177 |
| 178# A single DDR3 x64 interface (one command and address bus), with 179# default timings based on DDR3-1600 4 Gbit parts in an 8x8 180# configuration, which would amount to 4 Gbyte of memory. | 178# A single DDR3-1600 x64 channel (one command and address bus), with 179# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 180# an 8x8 configuration, amounting to 4 Gbyte of memory. |
| 181class DDR3_1600_x64(DRAMCtrl): 182 # 8x8 configuration, 8 devices each with an 8-bit interface 183 device_bus_width = 8 184 185 # DDR3 is a BL8 device 186 burst_length = 8 187 | 181class DDR3_1600_x64(DRAMCtrl): 182 # 8x8 configuration, 8 devices each with an 8-bit interface 183 device_bus_width = 8 184 185 # DDR3 is a BL8 device 186 burst_length = 8 187 |
| 188 # Each device has a page (row buffer) size of 1KB 189 # (this depends on the memory density) | 188 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) |
| 190 device_rowbuffer_size = '1kB' 191 192 # 8x8 configuration, so 8 devices 193 devices_per_rank = 8 194 195 # Use two ranks 196 ranks_per_channel = 2 197 198 # DDR3 has 8 banks in all configurations 199 banks_per_rank = 8 200 201 # 800 MHz 202 tCK = '1.25ns' 203 | 189 device_rowbuffer_size = '1kB' 190 191 # 8x8 configuration, so 8 devices 192 devices_per_rank = 8 193 194 # Use two ranks 195 ranks_per_channel = 2 196 197 # DDR3 has 8 banks in all configurations 198 banks_per_rank = 8 199 200 # 800 MHz 201 tCK = '1.25ns' 202 |
| 204 # DDR3-1600 11-11-11-28 | 203 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 204 tBURST = '5ns' 205 206 # DDR3-1600 11-11-11 |
| 205 tRCD = '13.75ns' 206 tCL = '13.75ns' 207 tRP = '13.75ns' 208 tRAS = '35ns' | 207 tRCD = '13.75ns' 208 tCL = '13.75ns' 209 tRP = '13.75ns' 210 tRAS = '35ns' |
| 211 tRRD = '6ns' 212 tXAW = '30ns' 213 activation_limit = 4 214 tRFC = '260ns' 215 |
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| 209 tWR = '15ns' | 216 tWR = '15ns' |
| 210 tRTP = '7.5ns' | |
| 211 | 217 |
| 212 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 213 # Note this is a BL8 DDR device. 214 tBURST = '5ns' | 218 # Greater of 4 CK or 7.5 ns 219 tWTR = '7.5ns' |
| 215 | 220 |
| 216 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 217 tRFC = '300ns' | 221 # Greater of 4 CK or 7.5 ns 222 tRTP = '7.5ns' |
| 218 | 223 |
| 219 # DDR3, <=85C, half for >85C | 224 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 225 tRTW = '2.5ns' 226 227 # <=85C, half for >85C |
| 220 tREFI = '7.8us' 221 | 228 tREFI = '7.8us' 229 |
| 222 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 223 tWTR = '7.5ns' | 230# A single DDR3-2133 x64 channel refining a selected subset of the 231# options for the DDR-1600 configuration, based on the same DDR3-1600 232# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 233# consistent across the two configurations. 234class DDR3_2133_x64(DDR3_1600_x64): 235 # 1066 MHz 236 tCK = '0.938ns' |
| 224 | 237 |
| 225 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 226 tRTW = '2.5ns' | 238 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 239 tBURST = '3.752ns' |
| 227 | 240 |
| 228 # Assume 5 CK for activate to activate for different banks 229 tRRD = '6.25ns' | 241 # DDR3-2133 14-14-14 242 tRCD = '13.09ns' 243 tCL = '13.09ns' 244 tRP = '13.09ns' 245 tRAS = '33ns' 246 tRRD = '5ns' 247 tXAW = '25ns' |
| 230 | 248 |
| 231 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 232 tXAW = '40ns' | 249# A single DDR4-2400 x64 channel (one command and address bus), with 250# timings based on a DDR4-2400 4 Gbit datasheet (Samsung K4A4G085WD) 251# in an 8x8 configuration, amounting to 4 Gbyte of memory. 252class DDR4_2400_x64(DRAMCtrl): 253 # 8x8 configuration, 8 devices each with an 8-bit interface 254 device_bus_width = 8 255 256 # DDR4 is a BL8 device 257 burst_length = 8 258 259 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 260 device_rowbuffer_size = '1kB' 261 262 # 8x8 configuration, so 8 devices 263 devices_per_rank = 8 264 265 # Use a single rank 266 ranks_per_channel = 1 267 268 # DDR4 has 16 banks (4 bank groups) in all 269 # configurations. Currently we do not capture the additional 270 # constraints incurred by the bank groups 271 banks_per_rank = 16 272 273 # 1200 MHz 274 tCK = '0.833ns' 275 276 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 277 tBURST = '3.333ns' 278 279 # DDR4-2400 17-17-17 280 tRCD = '14.16ns' 281 tCL = '14.16ns' 282 tRP = '14.16ns' 283 tRAS = '32ns' 284 285 # Here using the average of RRD_S and RRD_L 286 tRRD = '4.1ns' 287 tXAW = '21ns' |
| 233 activation_limit = 4 | 288 activation_limit = 4 |
| 289 tRFC = '260ns' |
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| 234 | 290 |
| 291 tWR = '15ns' |
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| 235 | 292 |
| 293 # Here using the average of WTR_S and WTR_L 294 tWTR = '5ns' 295 296 # Greater of 4 CK or 7.5 ns 297 tRTP = '7.5ns' 298 299 # Default read-to-write bus around to 2 CK, @1200 MHz = 1.666 ns 300 tRTW = '1.666ns' 301 302 # <=85C, half for >85C 303 tREFI = '7.8us' 304 |
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| 236# A single DDR3 x64 interface (one command and address bus), with 237# default timings based on DDR3-1333 4 Gbit parts in an 8x8 238# configuration, which would amount to 4 GByte of memory. This 239# configuration is primarily for comparing with DRAMSim2, and all the 240# parameters except ranks_per_channel are based on the DRAMSim2 config 241# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 242# to be manually set, depending on size of the memory to be 243# simulated. By default DRAMSim2 has 2048MB of memory with a single --- 235 unchanged lines hidden --- | 305# A single DDR3 x64 interface (one command and address bus), with 306# default timings based on DDR3-1333 4 Gbit parts in an 8x8 307# configuration, which would amount to 4 GByte of memory. This 308# configuration is primarily for comparing with DRAMSim2, and all the 309# parameters except ranks_per_channel are based on the DRAMSim2 config 310# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 311# to be manually set, depending on size of the memory to be 312# simulated. By default DRAMSim2 has 2048MB of memory with a single --- 235 unchanged lines hidden --- |