DRAMCtrl.py (10212:acc1131e01d6) DRAMCtrl.py (10216:52c869140fc2)
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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114 banks_per_rank = Param.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels = Param.Unsigned(1, "Number of channels")
119
120 # timing behaviour and constraints - all in nanoseconds
121
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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114 banks_per_rank = Param.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels = Param.Unsigned(1, "Number of channels")
119
120 # timing behaviour and constraints - all in nanoseconds
121
122 # the base clock period of the DRAM
123 tCK = Param.Latency("Clock period")
124
122 # the amount of time in nanoseconds from issuing an activate command
123 # to the data being available in the row buffer for a read/write
124 tRCD = Param.Latency("RAS to CAS delay")
125
126 # the time from issuing a read/write command to seeing the actual data
127 tCL = Param.Latency("CAS latency")
128
129 # minimum time between a precharge and subsequent activate

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190 devices_per_rank = 8
191
192 # Use two ranks
193 ranks_per_channel = 2
194
195 # DDR3 has 8 banks in all configurations
196 banks_per_rank = 8
197
125 # the amount of time in nanoseconds from issuing an activate command
126 # to the data being available in the row buffer for a read/write
127 tRCD = Param.Latency("RAS to CAS delay")
128
129 # the time from issuing a read/write command to seeing the actual data
130 tCL = Param.Latency("CAS latency")
131
132 # minimum time between a precharge and subsequent activate

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193 devices_per_rank = 8
194
195 # Use two ranks
196 ranks_per_channel = 2
197
198 # DDR3 has 8 banks in all configurations
199 banks_per_rank = 8
200
201 # 800 MHz
202 tCK = '1.25ns'
203
198 # DDR3-1600 11-11-11-28
199 tRCD = '13.75ns'
200 tCL = '13.75ns'
201 tRP = '13.75ns'
202 tRAS = '35ns'
203 tWR = '15ns'
204 tRTP = '7.5ns'
205

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251 devices_per_rank = 8
252
253 # Use two ranks
254 ranks_per_channel = 2
255
256 # DDR3 has 8 banks in all configurations
257 banks_per_rank = 8
258
204 # DDR3-1600 11-11-11-28
205 tRCD = '13.75ns'
206 tCL = '13.75ns'
207 tRP = '13.75ns'
208 tRAS = '35ns'
209 tWR = '15ns'
210 tRTP = '7.5ns'
211

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257 devices_per_rank = 8
258
259 # Use two ranks
260 ranks_per_channel = 2
261
262 # DDR3 has 8 banks in all configurations
263 banks_per_rank = 8
264
265 # 666 MHs
266 tCK = '1.5ns'
267
259 tRCD = '15ns'
260 tCL = '15ns'
261 tRP = '15ns'
262 tRAS = '36ns'
263 tWR = '15ns'
264 tRTP = '7.5ns'
265
266 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.

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302 devices_per_rank = 1
303
304 # Use a single rank
305 ranks_per_channel = 1
306
307 # LPDDR2-S4 has 8 banks in all configurations
308 banks_per_rank = 8
309
268 tRCD = '15ns'
269 tCL = '15ns'
270 tRP = '15ns'
271 tRAS = '36ns'
272 tWR = '15ns'
273 tRTP = '7.5ns'
274
275 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.

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311 devices_per_rank = 1
312
313 # Use a single rank
314 ranks_per_channel = 1
315
316 # LPDDR2-S4 has 8 banks in all configurations
317 banks_per_rank = 8
318
319 # 533 MHz
320 tCK = '1.876ns'
321
310 # Fixed at 15 ns
311 tRCD = '15ns'
312
313 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
314 tCL = '15ns'
315
316 # Pre-charge one bank 15 ns (all banks 18 ns)
317 tRP = '15ns'

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362 devices_per_rank = 1
363
364 # Use one rank for a one-high die stack
365 ranks_per_channel = 1
366
367 # WideIO has 4 banks in all configurations
368 banks_per_rank = 4
369
322 # Fixed at 15 ns
323 tRCD = '15ns'
324
325 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
326 tCL = '15ns'
327
328 # Pre-charge one bank 15 ns (all banks 18 ns)
329 tRP = '15ns'

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374 devices_per_rank = 1
375
376 # Use one rank for a one-high die stack
377 ranks_per_channel = 1
378
379 # WideIO has 4 banks in all configurations
380 banks_per_rank = 4
381
382 # 200 MHz
383 tCK = '5ns'
384
370 # WIO-200
371 tRCD = '18ns'
372 tCL = '18ns'
373 tRP = '18ns'
374 tRAS = '42ns'
375 tWR = '15ns'
376 # Read to precharge is same as the burst
377 tRTP = '20ns'

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416 devices_per_rank = 1
417
418 # Use a single rank
419 ranks_per_channel = 1
420
421 # LPDDR3 has 8 banks in all configurations
422 banks_per_rank = 8
423
385 # WIO-200
386 tRCD = '18ns'
387 tCL = '18ns'
388 tRP = '18ns'
389 tRAS = '42ns'
390 tWR = '15ns'
391 # Read to precharge is same as the burst
392 tRTP = '20ns'

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431 devices_per_rank = 1
432
433 # Use a single rank
434 ranks_per_channel = 1
435
436 # LPDDR3 has 8 banks in all configurations
437 banks_per_rank = 8
438
439 # 800 MHz
440 tCK = '1.25ns'
441
424 # Fixed at 15 ns
425 tRCD = '15ns'
426
427 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
428 tCL = '15ns'
429
430 tRAS = '42ns'
431 tWR = '15ns'

--- 29 unchanged lines hidden --- 		442 # Fixed at 15 ns
443 tRCD = '15ns'
444
445 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
446 tCL = '15ns'
447
448 tRAS = '42ns'
449 tWR = '15ns'

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