| DRAMCtrl.py (10210:793e5ff26e0b) | DRAMCtrl.py (10212:acc1131e01d6) |
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| 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 121 unchanged lines hidden (view full) --- 130 tRP = Param.Latency("Row precharge time") 131 132 # minimum time between an activate and a precharge to the same row 133 tRAS = Param.Latency("ACT to PRE delay") 134 135 # minimum time between a write data transfer and a precharge 136 tWR = Param.Latency("Write recovery time") 137 | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 121 unchanged lines hidden (view full) --- 130 tRP = Param.Latency("Row precharge time") 131 132 # minimum time between an activate and a precharge to the same row 133 tRAS = Param.Latency("ACT to PRE delay") 134 135 # minimum time between a write data transfer and a precharge 136 tWR = Param.Latency("Write recovery time") 137 |
| 138 # minimum time between a read and precharge command 139 tRTP = Param.Latency("Read to precharge") 140 |
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| 138 # time to complete a burst transfer, typically the burst length 139 # divided by two due to the DDR bus, but by making it a parameter 140 # it is easier to also evaluate SDR memories like WideIO. 141 # This parameter has to account for burst length. 142 # Read/Write requests with data size larger than one full burst are broken 143 # down into multiple requests in the controller 144 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 145 --- 47 unchanged lines hidden (view full) --- 193 banks_per_rank = 8 194 195 # DDR3-1600 11-11-11-28 196 tRCD = '13.75ns' 197 tCL = '13.75ns' 198 tRP = '13.75ns' 199 tRAS = '35ns' 200 tWR = '15ns' | 141 # time to complete a burst transfer, typically the burst length 142 # divided by two due to the DDR bus, but by making it a parameter 143 # it is easier to also evaluate SDR memories like WideIO. 144 # This parameter has to account for burst length. 145 # Read/Write requests with data size larger than one full burst are broken 146 # down into multiple requests in the controller 147 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 148 --- 47 unchanged lines hidden (view full) --- 196 banks_per_rank = 8 197 198 # DDR3-1600 11-11-11-28 199 tRCD = '13.75ns' 200 tCL = '13.75ns' 201 tRP = '13.75ns' 202 tRAS = '35ns' 203 tWR = '15ns' |
| 204 tRTP = '7.5ns' |
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| 201 202 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 203 # Note this is a BL8 DDR device. 204 tBURST = '5ns' 205 206 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 207 tRFC = '300ns' 208 --- 43 unchanged lines hidden (view full) --- 252 # DDR3 has 8 banks in all configurations 253 banks_per_rank = 8 254 255 tRCD = '15ns' 256 tCL = '15ns' 257 tRP = '15ns' 258 tRAS = '36ns' 259 tWR = '15ns' | 205 206 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 207 # Note this is a BL8 DDR device. 208 tBURST = '5ns' 209 210 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 211 tRFC = '300ns' 212 --- 43 unchanged lines hidden (view full) --- 256 # DDR3 has 8 banks in all configurations 257 banks_per_rank = 8 258 259 tRCD = '15ns' 260 tCL = '15ns' 261 tRP = '15ns' 262 tRAS = '36ns' 263 tWR = '15ns' |
| 264 tRTP = '7.5ns' |
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| 260 261 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 262 # Note this is a BL8 DDR device. 263 tBURST = '6ns' 264 265 tRFC = '160ns' 266 267 # DDR3, <=85C, half for >85C --- 41 unchanged lines hidden (view full) --- 309 tCL = '15ns' 310 311 # Pre-charge one bank 15 ns (all banks 18 ns) 312 tRP = '15ns' 313 314 tRAS = '42ns' 315 tWR = '15ns' 316 | 265 266 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 267 # Note this is a BL8 DDR device. 268 tBURST = '6ns' 269 270 tRFC = '160ns' 271 272 # DDR3, <=85C, half for >85C --- 41 unchanged lines hidden (view full) --- 314 tCL = '15ns' 315 316 # Pre-charge one bank 15 ns (all banks 18 ns) 317 tRP = '15ns' 318 319 tRAS = '42ns' 320 tWR = '15ns' 321 |
| 322 # 6 CK read to precharge delay 323 tRTP = '11.256ns' 324 |
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| 317 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 318 # Note this is a BL8 DDR device. 319 # Requests larger than 32 bytes are broken down into multiple requests 320 # in the controller 321 tBURST = '7.5ns' 322 323 # LPDDR2-S4, 4 Gbit 324 tRFC = '130ns' --- 35 unchanged lines hidden (view full) --- 360 banks_per_rank = 4 361 362 # WIO-200 363 tRCD = '18ns' 364 tCL = '18ns' 365 tRP = '18ns' 366 tRAS = '42ns' 367 tWR = '15ns' | 325 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 326 # Note this is a BL8 DDR device. 327 # Requests larger than 32 bytes are broken down into multiple requests 328 # in the controller 329 tBURST = '7.5ns' 330 331 # LPDDR2-S4, 4 Gbit 332 tRFC = '130ns' --- 35 unchanged lines hidden (view full) --- 368 banks_per_rank = 4 369 370 # WIO-200 371 tRCD = '18ns' 372 tCL = '18ns' 373 tRP = '18ns' 374 tRAS = '42ns' 375 tWR = '15ns' |
| 376 # Read to precharge is same as the burst 377 tRTP = '20ns' |
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| 368 369 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 370 # Note this is a BL4 SDR device. 371 tBURST = '20ns' 372 373 # WIO 8 Gb 374 tRFC = '210ns' 375 --- 39 unchanged lines hidden (view full) --- 415 tRCD = '15ns' 416 417 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 418 tCL = '15ns' 419 420 tRAS = '42ns' 421 tWR = '15ns' 422 | 378 379 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 380 # Note this is a BL4 SDR device. 381 tBURST = '20ns' 382 383 # WIO 8 Gb 384 tRFC = '210ns' 385 --- 39 unchanged lines hidden (view full) --- 425 tRCD = '15ns' 426 427 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 428 tCL = '15ns' 429 430 tRAS = '42ns' 431 tWR = '15ns' 432 |
| 433 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 434 tRTP = '7.5ns' 435 |
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| 423 # Pre-charge one bank 15 ns (all banks 18 ns) 424 tRP = '15ns' 425 426 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 427 # Note this is a BL8 DDR device. 428 # Requests larger than 32 bytes are broken down into multiple requests 429 # in the controller 430 tBURST = '5ns' --- 17 unchanged lines hidden --- | 436 # Pre-charge one bank 15 ns (all banks 18 ns) 437 tRP = '15ns' 438 439 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 440 # Note this is a BL8 DDR device. 441 # Requests larger than 32 bytes are broken down into multiple requests 442 # in the controller 443 tBURST = '5ns' --- 17 unchanged lines hidden --- |