| DRAMCtrl.py (10206:823f7fd1a82f) | DRAMCtrl.py (10210:793e5ff26e0b) |
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| 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 118 unchanged lines hidden (view full) --- 127 tCL = Param.Latency("CAS latency") 128 129 # minimum time between a precharge and subsequent activate 130 tRP = Param.Latency("Row precharge time") 131 132 # minimum time between an activate and a precharge to the same row 133 tRAS = Param.Latency("ACT to PRE delay") 134 | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 118 unchanged lines hidden (view full) --- 127 tCL = Param.Latency("CAS latency") 128 129 # minimum time between a precharge and subsequent activate 130 tRP = Param.Latency("Row precharge time") 131 132 # minimum time between an activate and a precharge to the same row 133 tRAS = Param.Latency("ACT to PRE delay") 134 |
| 135 # minimum time between a write data transfer and a precharge 136 tWR = Param.Latency("Write recovery time") 137 |
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| 135 # time to complete a burst transfer, typically the burst length 136 # divided by two due to the DDR bus, but by making it a parameter 137 # it is easier to also evaluate SDR memories like WideIO. 138 # This parameter has to account for burst length. 139 # Read/Write requests with data size larger than one full burst are broken 140 # down into multiple requests in the controller 141 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 142 --- 46 unchanged lines hidden (view full) --- 189 # DDR3 has 8 banks in all configurations 190 banks_per_rank = 8 191 192 # DDR3-1600 11-11-11-28 193 tRCD = '13.75ns' 194 tCL = '13.75ns' 195 tRP = '13.75ns' 196 tRAS = '35ns' | 138 # time to complete a burst transfer, typically the burst length 139 # divided by two due to the DDR bus, but by making it a parameter 140 # it is easier to also evaluate SDR memories like WideIO. 141 # This parameter has to account for burst length. 142 # Read/Write requests with data size larger than one full burst are broken 143 # down into multiple requests in the controller 144 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 145 --- 46 unchanged lines hidden (view full) --- 192 # DDR3 has 8 banks in all configurations 193 banks_per_rank = 8 194 195 # DDR3-1600 11-11-11-28 196 tRCD = '13.75ns' 197 tCL = '13.75ns' 198 tRP = '13.75ns' 199 tRAS = '35ns' |
| 200 tWR = '15ns' |
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| 197 198 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 199 # Note this is a BL8 DDR device. 200 tBURST = '5ns' 201 202 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 203 tRFC = '300ns' 204 --- 42 unchanged lines hidden (view full) --- 247 248 # DDR3 has 8 banks in all configurations 249 banks_per_rank = 8 250 251 tRCD = '15ns' 252 tCL = '15ns' 253 tRP = '15ns' 254 tRAS = '36ns' | 201 202 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 203 # Note this is a BL8 DDR device. 204 tBURST = '5ns' 205 206 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 207 tRFC = '300ns' 208 --- 42 unchanged lines hidden (view full) --- 251 252 # DDR3 has 8 banks in all configurations 253 banks_per_rank = 8 254 255 tRCD = '15ns' 256 tCL = '15ns' 257 tRP = '15ns' 258 tRAS = '36ns' |
| 259 tWR = '15ns' |
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| 255 256 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 257 # Note this is a BL8 DDR device. 258 tBURST = '6ns' 259 260 tRFC = '160ns' 261 262 # DDR3, <=85C, half for >85C --- 39 unchanged lines hidden (view full) --- 302 303 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 304 tCL = '15ns' 305 306 # Pre-charge one bank 15 ns (all banks 18 ns) 307 tRP = '15ns' 308 309 tRAS = '42ns' | 260 261 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 262 # Note this is a BL8 DDR device. 263 tBURST = '6ns' 264 265 tRFC = '160ns' 266 267 # DDR3, <=85C, half for >85C --- 39 unchanged lines hidden (view full) --- 307 308 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 309 tCL = '15ns' 310 311 # Pre-charge one bank 15 ns (all banks 18 ns) 312 tRP = '15ns' 313 314 tRAS = '42ns' |
| 315 tWR = '15ns' |
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| 310 311 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 312 # Note this is a BL8 DDR device. 313 # Requests larger than 32 bytes are broken down into multiple requests 314 # in the controller 315 tBURST = '7.5ns' 316 317 # LPDDR2-S4, 4 Gbit --- 35 unchanged lines hidden (view full) --- 353 # WideIO has 4 banks in all configurations 354 banks_per_rank = 4 355 356 # WIO-200 357 tRCD = '18ns' 358 tCL = '18ns' 359 tRP = '18ns' 360 tRAS = '42ns' | 316 317 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 318 # Note this is a BL8 DDR device. 319 # Requests larger than 32 bytes are broken down into multiple requests 320 # in the controller 321 tBURST = '7.5ns' 322 323 # LPDDR2-S4, 4 Gbit --- 35 unchanged lines hidden (view full) --- 359 # WideIO has 4 banks in all configurations 360 banks_per_rank = 4 361 362 # WIO-200 363 tRCD = '18ns' 364 tCL = '18ns' 365 tRP = '18ns' 366 tRAS = '42ns' |
| 367 tWR = '15ns' |
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| 361 362 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 363 # Note this is a BL4 SDR device. 364 tBURST = '20ns' 365 366 # WIO 8 Gb 367 tRFC = '210ns' 368 --- 37 unchanged lines hidden (view full) --- 406 407 # Fixed at 15 ns 408 tRCD = '15ns' 409 410 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 411 tCL = '15ns' 412 413 tRAS = '42ns' | 368 369 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 370 # Note this is a BL4 SDR device. 371 tBURST = '20ns' 372 373 # WIO 8 Gb 374 tRFC = '210ns' 375 --- 37 unchanged lines hidden (view full) --- 413 414 # Fixed at 15 ns 415 tRCD = '15ns' 416 417 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 418 tCL = '15ns' 419 420 tRAS = '42ns' |
| 421 tWR = '15ns' |
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| 414 415 # Pre-charge one bank 15 ns (all banks 18 ns) 416 tRP = '15ns' 417 418 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 419 # Note this is a BL8 DDR device. 420 # Requests larger than 32 bytes are broken down into multiple requests 421 # in the controller --- 18 unchanged lines hidden --- | 422 423 # Pre-charge one bank 15 ns (all banks 18 ns) 424 tRP = '15ns' 425 426 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 427 # Note this is a BL8 DDR device. 428 # Requests larger than 32 bytes are broken down into multiple requests 429 # in the controller --- 18 unchanged lines hidden --- |