1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 57 unchanged lines hidden (view full) --- 66class DRAMCtrl(AbstractMemory): 67 type = 'DRAMCtrl' 68 cxx_header = "mem/dram_ctrl.hh" 69 70 # single-ported on the system interface side, instantiate with a 71 # bus in front of the controller for multiple ports 72 port = SlavePort("Slave port") 73 |
74 # the basic configuration of the controller architecture, note 75 # that each entry corresponds to a burst for the specific DRAM 76 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 77 # the cacheline size or request/packet size |
78 write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 79 read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 80 81 # threshold in percent for when to forcefully trigger writes and 82 # start emptying the write buffer 83 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 84 85 # threshold in percentage for when to start writes if the read --- 653 unchanged lines hidden --- |