1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 97 unchanged lines hidden (view full) --- 106 # the physical organisation of the DRAM 107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 108 "device/chip") 109 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 111 "device/chip") 112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 113 ranks_per_channel = Param.Unsigned("Number of ranks per channel") |
114 115 # default to 0 bank groups per rank, indicating bank group architecture 116 # is not used 117 # update per memory class when bank group architecture is supported 118 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") |
119 banks_per_rank = Param.Unsigned("Number of banks per rank") 120 # only used for the address mapping as the controller by 121 # construction is a single channel and multiple controllers have 122 # to be instantiated for a multi-channel configuration 123 channels = Param.Unsigned(1, "Number of channels") 124 125 # timing behaviour and constraints - all in nanoseconds 126 --- 20 unchanged lines hidden (view full) --- 147 tRTP = Param.Latency("Read to precharge") 148 149 # time to complete a burst transfer, typically the burst length 150 # divided by two due to the DDR bus, but by making it a parameter 151 # it is easier to also evaluate SDR memories like WideIO. 152 # This parameter has to account for burst length. 153 # Read/Write requests with data size larger than one full burst are broken 154 # down into multiple requests in the controller |
155 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 156 # With bank group architectures, tBURST represents the CAS-to-CAS 157 # delay for bursts to different bank groups (tCCD_S) |
158 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 159 |
160 # CAS-to-CAS delay for bursts to the same bank group 161 # only utilized with bank group architectures; set to 0 for default case 162 # tBURST is equivalent to tCCD_S; no explicit parameter required 163 # for CAS-to-CAS delay for bursts to different bank groups 164 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 165 |
166 # time taken to complete one refresh cycle (N rows in all banks) 167 tRFC = Param.Latency("Refresh cycle time") 168 169 # refresh command interval, how often a "ref" command needs 170 # to be sent. It is 7.8 us for a 64ms refresh requirement 171 tREFI = Param.Latency("Refresh command interval") 172 173 # write-to-read, same rank turnaround penalty --- 6 unchanged lines hidden (view full) --- 180 # this does not correlate to a memory timing parameter and encompasses: 181 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 182 # different rank bus delay 183 tCS = Param.Latency("Rank to rank switching time") 184 185 # minimum row activate to row activate delay time 186 tRRD = Param.Latency("ACT to ACT delay") 187 |
188 # only utilized with bank group architectures; set to 0 for default case 189 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 190 |
191 # time window in which a maximum number of activates are allowed 192 # to take place, set to 0 to disable 193 tXAW = Param.Latency("X activation window") 194 activation_limit = Param.Unsigned("Max number of activates in window") 195 196 # Currently rolled into other params 197 ###################################################################### 198 --- 87 unchanged lines hidden (view full) --- 286 device_rowbuffer_size = '1kB' 287 288 # 8x8 configuration, so 8 devices 289 devices_per_rank = 8 290 291 # Use a single rank 292 ranks_per_channel = 1 293 |
294 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 295 # Set to 4 for x4, x8 case 296 bank_groups_per_rank = 4 297 |
298 # DDR4 has 16 banks (4 bank groups) in all 299 # configurations. Currently we do not capture the additional 300 # constraints incurred by the bank groups 301 banks_per_rank = 16 302 303 # 1200 MHz 304 tCK = '0.833ns' 305 306 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz |
307 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 308 # With bank group architectures, tBURST represents the CAS-to-CAS 309 # delay for bursts to different bank groups (tCCD_S) |
310 tBURST = '3.333ns' 311 |
312 # @2400 data rate, tCCD_L is 6 CK 313 # CAS-to-CAS delay for bursts to the same bank group 314 # tBURST is equivalent to tCCD_S; no explicit parameter required 315 # for CAS-to-CAS delay for bursts to different bank groups 316 tCCD_L = '5ns'; 317 |
318 # DDR4-2400 17-17-17 319 tRCD = '14.16ns' 320 tCL = '14.16ns' 321 tRP = '14.16ns' 322 tRAS = '32ns' 323 |
324 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns) 325 tRRD = '3.3ns' 326 327 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 328 tRRD_L = '4.9ns'; 329 |
330 tXAW = '21ns' 331 activation_limit = 4 332 tRFC = '260ns' 333 334 tWR = '15ns' 335 336 # Here using the average of WTR_S and WTR_L 337 tWTR = '5ns' --- 268 unchanged lines hidden --- |