1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 142 unchanged lines hidden (view full) --- 151 152 # time taken to complete one refresh cycle (N rows in all banks) 153 tRFC = Param.Latency("Refresh cycle time") 154 155 # refresh command interval, how often a "ref" command needs 156 # to be sent. It is 7.8 us for a 64ms refresh requirement 157 tREFI = Param.Latency("Refresh command interval") 158 |
159 # write-to-read, same rank turnaround penalty 160 tWTR = Param.Latency("Write to read, same rank switching time") |
161 |
162 # read-to-write, same rank turnaround penalty 163 tRTW = Param.Latency("Read to write, same rank switching time") |
164 |
165 # rank-to-rank bus delay penalty 166 # this does not correlate to a memory timing parameter and encompasses: 167 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 168 # different rank bus delay 169 tCS = Param.Latency("Rank to rank switching time") 170 |
171 # minimum row activate to row activate delay time 172 tRRD = Param.Latency("ACT to ACT delay") 173 174 # time window in which a maximum number of activates are allowed 175 # to take place, set to 0 to disable 176 tXAW = Param.Latency("X activation window") 177 activation_limit = Param.Unsigned("Max number of activates in window") 178 --- 43 unchanged lines hidden (view full) --- 222 tWR = '15ns' 223 224 # Greater of 4 CK or 7.5 ns 225 tWTR = '7.5ns' 226 227 # Greater of 4 CK or 7.5 ns 228 tRTP = '7.5ns' 229 |
230 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns |
231 tRTW = '2.5ns' 232 |
233 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 234 tCS = '2.5ns' 235 |
236 # <=85C, half for >85C 237 tREFI = '7.8us' 238 239# A single DDR3-2133 x64 channel refining a selected subset of the 240# options for the DDR-1600 configuration, based on the same DDR3-1600 241# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 242# consistent across the two configurations. 243class DDR3_2133_x64(DDR3_1600_x64): --- 56 unchanged lines hidden (view full) --- 300 tWR = '15ns' 301 302 # Here using the average of WTR_S and WTR_L 303 tWTR = '5ns' 304 305 # Greater of 4 CK or 7.5 ns 306 tRTP = '7.5ns' 307 |
308 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns |
309 tRTW = '1.666ns' 310 |
311 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 312 tCS = '1.666ns' 313 |
314 # <=85C, half for >85C 315 tREFI = '7.8us' 316 317# A single DDR3 x64 interface (one command and address bus), with 318# default timings based on DDR3-1333 4 Gbit parts in an 8x8 319# configuration, which would amount to 4 GByte of memory. This 320# configuration is primarily for comparing with DRAMSim2, and all the 321# parameters except ranks_per_channel are based on the DRAMSim2 config --- 38 unchanged lines hidden (view full) --- 360 tRFC = '160ns' 361 362 # DDR3, <=85C, half for >85C 363 tREFI = '7.8us' 364 365 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 366 tWTR = '7.5ns' 367 |
368 # Default same rank rd-to-wr bus turnaround to 2 CK, @666.66 MHz = 3 ns |
369 tRTW = '3ns' 370 |
371 # Default different rank bus delay to 2 CK, @666.66 MHz = 3 ns 372 tCS = '3ns' 373 |
374 tRRD = '6.0ns' 375 376 tXAW = '30ns' 377 activation_limit = 4 378 379 380# A single LPDDR2-S4 x32 interface (one command/address bus), with 381# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 --- 44 unchanged lines hidden (view full) --- 426 427 # LPDDR2-S4, 4 Gbit 428 tRFC = '130ns' 429 tREFI = '3.9us' 430 431 # Irrespective of speed grade, tWTR is 7.5 ns 432 tWTR = '7.5ns' 433 |
434 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns |
435 tRTW = '3.75ns' 436 |
437 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 438 tCS = '3.75ns' 439 |
440 # Activate to activate irrespective of density and speed grade 441 tRRD = '10.0ns' 442 443 # Irrespective of density, tFAW is 50 ns 444 tXAW = '50ns' 445 activation_limit = 4 446 447# A single WideIO x128 interface (one command and address bus), with --- 38 unchanged lines hidden (view full) --- 486 tRFC = '210ns' 487 488 # WIO 8 Gb, <=85C, half for >85C 489 tREFI = '3.9us' 490 491 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 492 tWTR = '15ns' 493 |
494 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns |
495 tRTW = '10ns' 496 |
497 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 498 tCS = '10ns' 499 |
500 # Activate to activate irrespective of density and speed grade 501 tRRD = '10.0ns' 502 503 # Two instead of four activation window 504 tXAW = '50ns' 505 activation_limit = 2 506 507# A single LPDDR3 x32 interface (one command/address bus), with --- 44 unchanged lines hidden (view full) --- 552 553 # LPDDR3, 4 Gb 554 tRFC = '130ns' 555 tREFI = '3.9us' 556 557 # Irrespective of speed grade, tWTR is 7.5 ns 558 tWTR = '7.5ns' 559 |
560 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns |
561 tRTW = '2.5ns' 562 |
563 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 564 tCS = '2.5ns' 565 |
566 # Activate to activate irrespective of density and speed grade 567 tRRD = '10.0ns' 568 569 # Irrespective of size, tFAW is 50 ns 570 tXAW = '50ns' 571 activation_limit = 4 |