318c318
< class DDR3_1600_x64(DRAMCtrl):
---
> class DDR3_1600_8x8(DRAMCtrl):
413c413
< class HMC_2500_x32(DDR3_1600_x64):
---
> class HMC_2500_1x32(DDR3_1600_8x8):
495c495
< class DDR3_2133_x64(DDR3_1600_x64):
---
> class DDR3_2133_8x8(DDR3_1600_8x8):
523,525c523,527
< # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16)
< # in an 4x16 configuration.
< class DDR4_2400_x64(DRAMCtrl):
---
> # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
> # in an 16x4 configuration.
> # Total channel capacity is 32GB
> # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
> class DDR4_2400_16x4(DRAMCtrl):
527c529
< device_size = '512MB'
---
> device_size = '1GB'
529,530c531,532
< # 4x16 configuration, 4 devices each with an 16-bit interface
< device_bus_width = 16
---
> # 16x4 configuration, 16 devices each with a 4-bit interface
> device_bus_width = 4
535,536c537,538
< # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
< device_rowbuffer_size = '2kB'
---
> # Each device has a page (row buffer) size of 512 byte (1K columns x4)
> device_rowbuffer_size = '512B'
538,539c540,541
< # 4x16 configuration, so 4 devices
< devices_per_rank = 4
---
> # 16x4 configuration, so 16 devices
> devices_per_rank = 16
545,546c547,548
< # Set to 2 for x16 case
< bank_groups_per_rank = 2
---
> # Set to 4 for x4 case
> bank_groups_per_rank = 4
551c553
< banks_per_rank = 8
---
> banks_per_rank = 16
565c567
< tBURST = '3.333ns'
---
> tBURST = '3.332ns'
573,577c575,579
< # DDR4-2400 16-16-16
< tRCD = '13.32ns'
< tCL = '13.32ns'
< tRP = '13.32ns'
< tRAS = '35ns'
---
> # DDR4-2400 17-17-17
> tRCD = '14.16ns'
> tCL = '14.16ns'
> tRP = '14.16ns'
> tRAS = '32ns'
579,580c581,582
< # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
< tRRD = '5.3ns'
---
> # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
> tRRD = '3.332ns'
582,583c584,585
< # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
< tRRD_L = '6.4ns';
---
> # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
> tRRD_L = '4.9ns';
585c587,588
< tXAW = '30ns'
---
> # tFAW for 512B page is MAX(16 CK, 13ns)
> tXAW = '13.328ns'
587c590,591
< tRFC = '260ns'
---
> # tRFC is 350ns
> tRFC = '350ns'
610c614,616
< tXS = '120ns'
---
> # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
> # tRFC + 10ns = 340ns
> tXS = '340ns'
613,616c619,622
< IDD0 = '70mA'
< IDD02 = '4.6mA'
< IDD2N = '50mA'
< IDD3N = '67mA'
---
> IDD0 = '43mA'
> IDD02 = '3mA'
> IDD2N = '34mA'
> IDD3N = '38mA'
618,623c624,629
< IDD4W = '302mA'
< IDD4R = '230mA'
< IDD5 = '192mA'
< IDD3P1 = '44mA'
< IDD2P1 = '32mA'
< IDD6 = '20mA'
---
> IDD4W = '103mA'
> IDD4R = '110mA'
> IDD5 = '250mA'
> IDD3P1 = '32mA'
> IDD2P1 = '25mA'
> IDD6 = '30mA'
626a633,701
> # A single DDR4-2400 x64 channel (one command and address bus), with
> # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
> # in an 8x8 configuration.
> # Total channel capacity is 16GB
> # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
> class DDR4_2400_8x8(DDR4_2400_16x4):
> # 8x8 configuration, 8 devices each with an 8-bit interface
> device_bus_width = 8
>
> # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
> device_rowbuffer_size = '1kB'
>
> # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
> tRRD_L = '4.9ns';
>
> tXAW = '21ns'
>
> # Current values from datasheet
> IDD0 = '48mA'
> IDD3N = '43mA'
> IDD4W = '123mA'
> IDD4R = '135mA'
> IDD3P1 = '37mA'
>
> # A single DDR4-2400 x64 channel (one command and address bus), with
> # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
> # in an 4x16 configuration.
> # Total channel capacity is 4GB
> # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
> class DDR4_2400_4x16(DDR4_2400_16x4):
> # 4x16 configuration, 4 devices each with an 16-bit interface
> device_bus_width = 16
>
> # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
> device_rowbuffer_size = '2kB'
>
> # 4x16 configuration, so 4 devices
> devices_per_rank = 4
>
> # Single rank for x16
> ranks_per_channel = 1
>
> # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
> # Set to 2 for x16 case
> bank_groups_per_rank = 2
>
> # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
> # configurations). Currently we do not capture the additional
> # constraints incurred by the bank groups
> banks_per_rank = 8
>
> # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
> tRRD = '5.3ns'
>
> # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
> tRRD_L = '6.4ns';
>
> tXAW = '30ns'
>
> # Current values from datasheet
> IDD0 = '80mA'
> IDD02 = '4mA'
> IDD2N = '34mA'
> IDD3N = '47mA'
> IDD4W = '228mA'
> IDD4R = '243mA'
> IDD5 = '280mA'
> IDD3P1 = '41mA'
>
630c705
< class LPDDR2_S4_1066_x32(DRAMCtrl):
---
> class LPDDR2_S4_1066_1x32(DRAMCtrl):
729c804
< class WideIO_200_x128(DRAMCtrl):
---
> class WideIO_200_1x128(DRAMCtrl):
798c873
< class LPDDR3_1600_x32(DRAMCtrl):
---
> class LPDDR3_1600_1x32(DRAMCtrl):
898c973
< class GDDR5_4000_x64(DRAMCtrl):
---
> class GDDR5_4000_2x32(DRAMCtrl):
982c1057
< class HBM_1000_4H_x128(DRAMCtrl):
---
> class HBM_1000_4H_1x128(DRAMCtrl):
1071c1146
< class HBM_1000_4H_x64(HBM_1000_4H_x128):
---
> class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
< class DDR3_1600_x64(DRAMCtrl):
---
> class DDR3_1600_8x8(DRAMCtrl):
413c413
< class HMC_2500_x32(DDR3_1600_x64):
---
> class HMC_2500_1x32(DDR3_1600_8x8):
495c495
< class DDR3_2133_x64(DDR3_1600_x64):
---
> class DDR3_2133_8x8(DDR3_1600_8x8):
523,525c523,527
< # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16)
< # in an 4x16 configuration.
< class DDR4_2400_x64(DRAMCtrl):
---
> # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
> # in an 16x4 configuration.
> # Total channel capacity is 32GB
> # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
> class DDR4_2400_16x4(DRAMCtrl):
527c529
< device_size = '512MB'
---
> device_size = '1GB'
529,530c531,532
< # 4x16 configuration, 4 devices each with an 16-bit interface
< device_bus_width = 16
---
> # 16x4 configuration, 16 devices each with a 4-bit interface
> device_bus_width = 4
535,536c537,538
< # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
< device_rowbuffer_size = '2kB'
---
> # Each device has a page (row buffer) size of 512 byte (1K columns x4)
> device_rowbuffer_size = '512B'
538,539c540,541
< # 4x16 configuration, so 4 devices
< devices_per_rank = 4
---
> # 16x4 configuration, so 16 devices
> devices_per_rank = 16
545,546c547,548
< # Set to 2 for x16 case
< bank_groups_per_rank = 2
---
> # Set to 4 for x4 case
> bank_groups_per_rank = 4
551c553
< banks_per_rank = 8
---
> banks_per_rank = 16
565c567
< tBURST = '3.333ns'
---
> tBURST = '3.332ns'
573,577c575,579
< # DDR4-2400 16-16-16
< tRCD = '13.32ns'
< tCL = '13.32ns'
< tRP = '13.32ns'
< tRAS = '35ns'
---
> # DDR4-2400 17-17-17
> tRCD = '14.16ns'
> tCL = '14.16ns'
> tRP = '14.16ns'
> tRAS = '32ns'
579,580c581,582
< # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
< tRRD = '5.3ns'
---
> # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
> tRRD = '3.332ns'
582,583c584,585
< # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
< tRRD_L = '6.4ns';
---
> # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
> tRRD_L = '4.9ns';
585c587,588
< tXAW = '30ns'
---
> # tFAW for 512B page is MAX(16 CK, 13ns)
> tXAW = '13.328ns'
587c590,591
< tRFC = '260ns'
---
> # tRFC is 350ns
> tRFC = '350ns'
610c614,616
< tXS = '120ns'
---
> # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
> # tRFC + 10ns = 340ns
> tXS = '340ns'
613,616c619,622
< IDD0 = '70mA'
< IDD02 = '4.6mA'
< IDD2N = '50mA'
< IDD3N = '67mA'
---
> IDD0 = '43mA'
> IDD02 = '3mA'
> IDD2N = '34mA'
> IDD3N = '38mA'
618,623c624,629
< IDD4W = '302mA'
< IDD4R = '230mA'
< IDD5 = '192mA'
< IDD3P1 = '44mA'
< IDD2P1 = '32mA'
< IDD6 = '20mA'
---
> IDD4W = '103mA'
> IDD4R = '110mA'
> IDD5 = '250mA'
> IDD3P1 = '32mA'
> IDD2P1 = '25mA'
> IDD6 = '30mA'
626a633,701
> # A single DDR4-2400 x64 channel (one command and address bus), with
> # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
> # in an 8x8 configuration.
> # Total channel capacity is 16GB
> # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
> class DDR4_2400_8x8(DDR4_2400_16x4):
> # 8x8 configuration, 8 devices each with an 8-bit interface
> device_bus_width = 8
>
> # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
> device_rowbuffer_size = '1kB'
>
> # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
> tRRD_L = '4.9ns';
>
> tXAW = '21ns'
>
> # Current values from datasheet
> IDD0 = '48mA'
> IDD3N = '43mA'
> IDD4W = '123mA'
> IDD4R = '135mA'
> IDD3P1 = '37mA'
>
> # A single DDR4-2400 x64 channel (one command and address bus), with
> # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
> # in an 4x16 configuration.
> # Total channel capacity is 4GB
> # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
> class DDR4_2400_4x16(DDR4_2400_16x4):
> # 4x16 configuration, 4 devices each with an 16-bit interface
> device_bus_width = 16
>
> # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
> device_rowbuffer_size = '2kB'
>
> # 4x16 configuration, so 4 devices
> devices_per_rank = 4
>
> # Single rank for x16
> ranks_per_channel = 1
>
> # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
> # Set to 2 for x16 case
> bank_groups_per_rank = 2
>
> # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
> # configurations). Currently we do not capture the additional
> # constraints incurred by the bank groups
> banks_per_rank = 8
>
> # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
> tRRD = '5.3ns'
>
> # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
> tRRD_L = '6.4ns';
>
> tXAW = '30ns'
>
> # Current values from datasheet
> IDD0 = '80mA'
> IDD02 = '4mA'
> IDD2N = '34mA'
> IDD3N = '47mA'
> IDD4W = '228mA'
> IDD4R = '243mA'
> IDD5 = '280mA'
> IDD3P1 = '41mA'
>
630c705
< class LPDDR2_S4_1066_x32(DRAMCtrl):
---
> class LPDDR2_S4_1066_1x32(DRAMCtrl):
729c804
< class WideIO_200_x128(DRAMCtrl):
---
> class WideIO_200_1x128(DRAMCtrl):
798c873
< class LPDDR3_1600_x32(DRAMCtrl):
---
> class LPDDR3_1600_1x32(DRAMCtrl):
898c973
< class GDDR5_4000_x64(DRAMCtrl):
---
> class GDDR5_4000_2x32(DRAMCtrl):
982c1057
< class HBM_1000_4H_x128(DRAMCtrl):
---
> class HBM_1000_4H_1x128(DRAMCtrl):
1071c1146
< class HBM_1000_4H_x64(HBM_1000_4H_x128):
---
> class HBM_1000_4H_1x64(HBM_1000_4H_1x128):