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> # Copyright (c) 2015 The University of Bologna
43a45
> # Erfan Azarkhish
385,386c387,388
< # [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
< # Hybrid Memory Cube (E. Azarkhish et. al)
---
> # [2] High performance AXI-4.0 based interconnect for extensible smart memory
> # cubes (E. Azarkhish et. al)
400,401c402,403
< # This configuration includes the latencies from the DRAM to the logic layer of
< # the HMC
---
> # This configuration includes the latencies from the DRAM to the logic layer
> # of the HMC
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< # activation limit is set to 0 since there are only 2 banks per vault layer.
---
> # activation limit is set to 0 since there are only 2 banks per vault
> # layer.
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< # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8
< # ns (Assumption)
---
> # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
> # 0.8 ns (Assumption)
459,462c462,467
< # Set default controller parameters
< page_policy = 'close'
< write_buffer_size = 8
< read_buffer_size = 8
---
> # The default page policy in the vault controllers is simple closed page
> # [2] nevertheless 'close' policy opens and closes the row multiple times
> # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
> page_policy = 'close_adaptive'
>
> # RoCoRaBaCh resembles the default address mapping in HMC
465a471,481
> # These parameters do not directly correlate with buffer_size in real
> # hardware. Nevertheless, their value has been tuned to achieve a
> # bandwidth similar to the cycle-accurate model in [2]
> write_buffer_size = 32
> read_buffer_size = 32
>
> # The static latency of the vault controllers is estimated to be smaller
> # than a full DRAM channel controller
> static_backend_latency='4ns'
> static_frontend_latency='4ns'
>
> # Copyright (c) 2015 The University of Bologna
43a45
> # Erfan Azarkhish
385,386c387,388
< # [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
< # Hybrid Memory Cube (E. Azarkhish et. al)
---
> # [2] High performance AXI-4.0 based interconnect for extensible smart memory
> # cubes (E. Azarkhish et. al)
400,401c402,403
< # This configuration includes the latencies from the DRAM to the logic layer of
< # the HMC
---
> # This configuration includes the latencies from the DRAM to the logic layer
> # of the HMC
444c446,447
< # activation limit is set to 0 since there are only 2 banks per vault layer.
---
> # activation limit is set to 0 since there are only 2 banks per vault
> # layer.
452,453c455,456
< # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8
< # ns (Assumption)
---
> # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
> # 0.8 ns (Assumption)
459,462c462,467
< # Set default controller parameters
< page_policy = 'close'
< write_buffer_size = 8
< read_buffer_size = 8
---
> # The default page policy in the vault controllers is simple closed page
> # [2] nevertheless 'close' policy opens and closes the row multiple times
> # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
> page_policy = 'close_adaptive'
>
> # RoCoRaBaCh resembles the default address mapping in HMC
465a471,481
> # These parameters do not directly correlate with buffer_size in real
> # hardware. Nevertheless, their value has been tuned to achieve a
> # bandwidth similar to the cycle-accurate model in [2]
> write_buffer_size = 32
> read_buffer_size = 32
>
> # The static latency of the vault controllers is estimated to be smaller
> # than a full DRAM channel controller
> static_backend_latency='4ns'
> static_frontend_latency='4ns'
>